公开(公告)号：KR1020010053771A

公开(公告)日：2001-07-02

申请号：KR1019990054279

申请日：1999-12-01

Applicant: 한국전자통신연구원

Inventor： 김해천 ,  양전욱 ,  곽명현 ,  문재경 ,  임종원 ,  이재진

IPC: H01L21/306

Abstract: PURPOSE: A method for photoelectrochemical etching of a semiconductor using an energy band bending is provided to improve an etching speed for the third group-nitrides by using a diluted etching solution. CONSTITUTION: An etching mask(3) is formed on a predetermined portion of a substrate(1). A resistance contact portion(4) is formed at one part of the substrate(1). An electric power is applied to the resistant contact portion(4). An insulating layer(6) is formed in order not to expose a connection portion between the resistance contact portion(4) and the power. The substrate(1) and the other electrode connected with the power source are soaked into an etching solution(11). A well is formed on a surface of the substrate(1) by applying the power to the substrate(1). An etching process is performed by irradiating the light larger than an energy gap of the substrate(1).

Abstract translation: 目的：提供使用能带弯曲对半导体进行光电化学蚀刻的方法，以通过使用稀释蚀刻溶液来提高第三组氮化物的蚀刻速度。 构成：在基板（1）的预定部分上形成蚀刻掩模（3）。 电阻接触部分（4）形成在衬底（1）的一部分处。 电力施加到电阻接触部分（4）上。 为了不暴露电阻接触部分（4）和电源之间的连接部分，形成绝缘层（6）。 将衬底（1）和与电源连接的另一电极浸入蚀刻溶液（11）中。 通过向基板（1）施加电力，在基板（1）的表面上形成阱。 通过照射比基板（1）的能隙大的光来进行蚀刻处理。

公开(公告)号：KR100317128B1

公开(公告)日：2001-12-24

申请号：KR1019990053886

申请日：1999-11-30

Applicant: 한국전자통신연구원

Inventor： 문재경 ,  김해천 ,  곽명현 ,  이재진 ,  임종원

IPC: H01L29/78

Abstract: 본발명은동작시채널층에발생하는열을효율적으로방출시키기위한전계효과트랜지스터및 그제조방법에관한것이다. 본발명에의한전계효과트랜지스터는소오스전극상에금 범프를형성하여플립칩형태로본딩하여패키징함으로써소자의성능및 신뢰성악화를방지할수 있도록한 것이다.

公开(公告)号：KR100311740B1

公开(公告)日：2001-10-12

申请号：KR1019990054279

申请日：1999-12-01

Applicant: 한국전자통신연구원

Inventor： 김해천 ,  양전욱 ,  곽명현 ,  문재경 ,  임종원 ,  이재진

IPC: H01L21/306

Abstract: 본발명은 III족질화물(Group III-nitrides)의식각방법에있어서기존의방법으로식각되지않는 p-형의기판을식각할수 있도록하고식각의효율을개선한에너지대구부러짐을이용한반도체의광전화학적식각방법에관한것이다. 본발명은 III족질화물의기판에저항성접촉을형성한뒤 역바어스전압을인가하여식각용액과접촉된반도체기판표면에홀(hole)의전위우물을형성하여파장이짧은빛의조사에의해생성된홀이기판의표면에축적되도록하므로써기판의산화에기여하도록하여식각효율을높인다. 따라서본 발명은 p-GaN 의식각을가능하게할 뿐아니라 n-GaN 의식각율을높일수 있으며, 역바이어스전압을변화시킴으로써식각속도를조절할수 있다.

公开(公告)号：KR1020010048979A

公开(公告)日：2001-06-15

申请号：KR1019990053886

申请日：1999-11-30

Applicant: 한국전자통신연구원

Inventor： 문재경 ,  김해천 ,  곽명현 ,  이재진 ,  임종원

IPC: H01L29/78

Abstract: PURPOSE: A method for manufacturing a field effect transistor is provided to efficiently radiate a lot of quantity of heat generated in a channel layer, and to reduce parasitic inductance by a bonding wire. CONSTITUTION: A channel layer is formed on a semiconductor substrate. A source electrode, a drain electrode and a gate electrode are formed on the channel layer. An insulating layer is formed on the channel layer, the source electrode, the drain electrode and the gate electrode. A bump composed of a conductive material is formed on the source electrode so that a part of the bump is buried in the insulating layer and the rest of the bump is protruded from the insulating layer.

Abstract translation: 目的：提供一种用于制造场效应晶体管的方法，以有效地辐射在沟道层中产生的大量热量，并且通过接合线来减少寄生电感。 构成：在半导体衬底上形成沟道层。 在沟道层上形成源电极，漏电极和栅电极。 在沟道层，源电极，漏电极和栅电极上形成绝缘层。 在源电极上形成由导电材料构成的凸块，使得凸块的一部分埋在绝缘层中，其余的凸块从绝缘层突出。