中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

17 records (took 0.019 seconds)

    VME버스시스템의 블록전송모드용 어드레스 발생회로
    2.
    发明授权
    VME버스시스템의 블록전송모드용 어드레스 발생회로 失效
    VME中的地址锁定和计数器电路

    公开(公告)号：KR1019930002790B1

    公开(公告)日：1993-04-10

    申请号：KR1019900021866

    申请日：1990-12-26

    Applicant: 한국전자통신연구원

    Inventor： 김중배 ,  김길호 ,  구교선 ,  안희일

    IPC: G06F13/40

    Abstract: The address generator circuit for transmitting data at a block unit to improve data transmission rate comprises a decoder (2) for receiving a 32 bit address signal and an address modifier code (AM code) from a master (1) of the versa module Europe (VME) bus system to output a block transmission mode signal (BLKMD) and a selecting signal (SLCTED), an address buffer (3) for outputting the uppermost 24 bit address if in block transmission mode and outputting the 32 bit address if not in block transmission mode, and an address latch and counter (4) for receiving the block transmission mode signal, the selecting signal and a lowermost 7 bit address to output a variable output address (OA) according to the input of a longword signal (LWORD) and counter clock (CNTCLK).

    Abstract translation: 用于以块为单位发送数据以提高数据传输速率的地址发生器电路包括：解码器（2），用于从反模块欧洲的主（1）接收32位地址信号和地址修改码（AM码） VME）总线系统输出块传输模式信号（BLKMD）和选择信号（SLCTED），地址缓冲器（3），用于在块传输模式下输出最高的24位地址，并且如果不在块中则输出32位地址 传输模式，以及用于接收块传输模式信号的地址锁存和计数器（4），选择信号和最低的7位地址，以根据长字信号（LWORD）的输入输出可变输出地址（OA），以及 计时器（CNTCLK）。

    변형에 기인한 자기양자점을 이용한 단전자 트랜지스터
    5.
    发明授权
    변형에 기인한 자기양자점을 이용한 단전자 트랜지스터 失效
    변형에기인한자기양자점을이용한단전자트랜스터터

    公开(公告)号：KR100399055B1

    公开(公告)日：2003-09-26

    申请号：KR1020010047548

    申请日：2001-08-07

    Applicant: 한국전자통신연구원

    Inventor： 김길호

    IPC: H01L29/778

    Abstract: PURPOSE: A single electron transistor using strain-induced self-assembled quantum dots is provided to shorten a size of quantum dot according to an electron beam lithography method and reduce a number of gates for controlling electrons passing the quantum dots. CONSTITUTION: A hetero junction structure(20) is formed with a non-doped GaAs buffer layer(11), the first AlGaAs quantum barrier layer(12a), the first GaAs quantum well layer(13a), an InAs self-quantum dot(14), the second GaAs quantum well layer(13b), the second AlGaAs quantum barrier layer(12b), an AlGaAs doped layer(15), and a capping layer(16). The hetero junction structure(20) is formed by using a semiconductor layer growth method such as a molecular beam epitaxy method and a metal organic chemical vapor deposition method.

    Abstract translation: 目的：提供使用应变诱导的自组装量子点的单电子晶体管，以根据电子束光刻方法缩小量子点的尺寸，并减少用于控制通过量子点的电子的栅极的数量。 （11），第一AlGaAs量子势垒层（12a），第一GaAs量子阱层（13a），InAs自量子点（13），第二GaAs量子阱层 14），第二GaAs量子阱层（13b），第二AlGaAs量子势垒层（12b），AlGaAs掺杂层（15）和覆盖层（16）。 异质结结构（20）通过使用诸如分子束外延法和金属有机化学气相沉积法的半导体层生长方法来形成。

    변형에 기인한 자기양자점을 이용한 단전자 트랜지스터
    6.
    发明公开
    변형에 기인한 자기양자점을 이용한 단전자 트랜지스터 失效
    使用应变诱导自组装量子点的单电子晶体管

    公开(公告)号：KR1020030013192A

    公开(公告)日：2003-02-14

    申请号：KR1020010047548

    申请日：2001-08-07

    Applicant: 한국전자통신연구원

    Inventor： 김길호

    IPC: H01L29/778

    Abstract: PURPOSE: A single electron transistor using strain-induced self-assembled quantum dots is provided to shorten a size of quantum dot according to an electron beam lithography method and reduce a number of gates for controlling electrons passing the quantum dots. CONSTITUTION: A hetero junction structure(20) is formed with a non-doped GaAs buffer layer(11), the first AlGaAs quantum barrier layer(12a), the first GaAs quantum well layer(13a), an InAs self-quantum dot(14), the second GaAs quantum well layer(13b), the second AlGaAs quantum barrier layer(12b), an AlGaAs doped layer(15), and a capping layer(16). The hetero junction structure(20) is formed by using a semiconductor layer growth method such as a molecular beam epitaxy method and a metal organic chemical vapor deposition method.

    Abstract translation: 目的：提供使用应变诱导自组装量子点的单电子晶体管，以根据电子束光刻方法缩短量子点的尺寸，并减少用于控制经过量子点的电子的数量的栅极。 构成：异质结结构（20）形成有非掺杂GaAs缓冲层（11），第一AlGaAs量子势垒层（12a），第一GaAs量子阱层（13a），InAs自量子点（ 14），第二GaAs量子阱层（13b），第二AlGaAs量子势垒层（12b），AlGaAs掺杂层（15）和覆盖层（16）。 通过使用分子束外延法和金属有机化学气相沉积法等半导体层生长法形成异质结结构（20）。

    32비트 마이크로 프로세서를 이용한 64비트 데이타전송회로
    8.
    发明授权
    32비트 마이크로 프로세서를 이용한 64비트 데이타전송회로 失效
    64位数据传输电路采用32位微处理器

    公开(公告)号：KR1019920009452B1

    公开(公告)日：1992-10-16

    申请号：KR1019900021868

    申请日：1990-12-26

    Applicant: 한국전자통신연구원

    Inventor： 김중배 ,  김길호 ,  구교선 ,  안희일 ,  송일현

    IPC: G06F13/38

    Abstract: The circuit is for transmitting 64 bit data using 32 bit microprocessor to improve the efficiency of buses and the speed of operation. It includes a 32-bit microprocessor (1) for transmitting and receiving data by 32 bits to and from a data bus (DATA BUS) through a bus (2), a control register (3) for generating a 64 bit signal (64TR) according to the 1 bit signal from the the microprocessor (1), an address decoder (4), a local memory controller (5) for generating data acknowledge signal (LMDTACK), and local memory section (6) composed of two banks (Bank0,Bank1).

    Abstract translation: 该电路用于使用32位微处理器传输64位数据，以提高总线的效率和运行速度。 它包括一个32位微处理器（1），用于通过总线（2）向数据总线（DATA BUS）发送和从数据总线（DATA BUS）发送和接收数据，用于产生64位信号（64TR）的控制寄存器（3） 根据来自微处理器（1）的1位信号，地址解码器（4），用于产生数据确认信号（LMDTACK）的本地存储器控制器（5）和由两个存储体组成的本地存储器部分（6） ，Bank1的）。

Patent Agency Ranking