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1.发明授权자체 라우팅(Self-routing) 방식을 이용한 디지틀이동통신 제어국의 패킷교환 처리장치 및 방법 失效PACKET SWITCHING AND ITS METHOD OF MOBILE COMMUNICATION CONTROL STATION OF SELF ROUTING
公开(公告)号：KR1019960011971B1
公开(公告)日：1996-09-06
申请号：KR1019930027113
申请日：1993-12-09
Applicant: 한국전자통신연구원
Abstract: a plurality of packet router connecting apparatus 10 including a packet data processing section, a transmitting section and a receiving section for outputting a parallel segment of N-bytes unit of a packet into a packet bus part according to a control signal after storing packet data of serial type to convert them into the packet data of parallel type which is transmitted from each subsystem in a control station; a packet bus control device including a bus control section and a serial communication connection section for accessing a bus-using right in the related packet router connecting apparatus in case of being packet data by sequentially checking the packet router connecting apparatus; a packet bus means establishing the each packet router connecting apparatus and the packet bus control device and slots inserting a data bus and a control signal bus of N bytes, the packet router connecting apparatus and the packet bus control device.
Abstract translation: 包括分组数据处理部分，发送部分和接收部分的多个分组路由器连接装置10，用于在存储分组数据的分组数据之后，根据控制信号将分组的N字节单位的并行段输出到分组总线部分 串行类型将其转换成从控制站中的每个子系统发送的并行类型的数据包; 分组总线控制装置，包括总线控制部分和串行通信连接部分，用于通过顺序地检查分组路由器连接装置，在分组数据的情况下访问相关分组路由器连接装置中的总线使用权限; 分组总线意味着建立每个分组路由器连接装置和分组总线控制装置以及插入N字节的数据总线和控制信号总线的插槽，分组路由器连接装置和分组总线控制装置。
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2.发明公开패킷교환 시스템에서의 패킷데이타 입출력 제어방법(Method for Controling Input/Output Of Packet Data On Packet Switching System) 失效分组交换系统（分组交换系统）中分组数据I / O的控制方法
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公开(公告)号：KR1019950022488A
公开(公告)日：1995-07-28
申请号：KR1019930030027
申请日：1993-12-27
Applicant: 한국전자통신연구원
Abstract: 본 발명은 패킷교환 기능을 필요로 하는 데이타 통신 장치, 이동 통신 기지국 장치 또는 교환장치등에서 고속데이타 처리, 프로토콜 처리 및 다양한 부호화 형태등을 수요하는 패킷접속 장치를 제공하는데 그 목적이 있으며, 상기 목적을 달성하기 위하여 본 발명은, 부호화 및 선로 접속부(*1), HDLC처리부(*2), 로직 처리부(*4), 패킷 데이타 저장부(*5), 메모리부(*3)를 구비한 다수의 통신채널 보드와, 패킷버스 접속부(*6)를 구비하여 고속 데이타 처리, 프로토콜 및 다양한 부호화 형태처리등을 수용한다.
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公开(公告)号：KR100129148B1
公开(公告)日：1998-04-08
申请号：KR1019940036347
申请日：1994-12-23
Applicant: 한국전자통신연구원
IPC: H04L7/033
Abstract: Disclosed is a time information transmittance circuit for a digital communication network including an 1PPS generation time calculation circuit which measures the delay time between predetermined time slots generated at the shortest time after the transfer state of the 1PPS clock is generated when a clock signal is transmitted through a predetermined time slots of E1 frame, and 1PPS transfer information and TOD information transmittance circuit which transmits an 1PPS transfer information and a TOD information output from the 1PPS generation time calculation circuit through a predetermined time slots of E1 frame. Thus, a soft-handoff function can be smoothly performed.
Abstract translation: 公开了一种数字通信网络的时间信息透射电路，包括1PPS生成时间计算电路，其测量在通过时钟信号传输之后产生1PPS时钟的传送状态之后的最短时间产生的预定时隙之间的延迟时间 E1帧的预定时隙和1PPS传送信息和TOD信息透射电路，其通过E1帧的预定时隙发送从1PPS生成时间计算电路输出的1PPS传送信息和TOD信息。 因此，可以平滑地执行软切换功能。
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5.发明授权패킷교환 시스템에서의 패킷데이타 입출력 제어방법(Method for Controling Input/Output Of Packet Data On Packet Switching System) 失效用于控制分组数据在分组交换系统上的输入/输出的方法
公开(公告)号：KR100126577B1
公开(公告)日：1998-04-03
申请号：KR1019940023649
申请日：1994-09-16
Applicant: 한국전자통신연구원
Inventor： 송일현
IPC: H04L12/40 , H04L12/801 , H04L12/24 , H04L12/70
Abstract: The initialization of the input/output counter at the initial situation in the process of controlling the input/output just before packet exchanging is implemented by a microprocessor part(10)(S1,S2). In case of receiving the data exchanging start signal from the packet exchanging main control unit(1), the input/output counter about the data storage block is increased(S3,S4). In case that the value of input counter which represents the data volume stored at the data storage block and that of output counter which represents the data volume read from the data storage block and emitted at the queueing state in the process of input/output right after the next packet exchanging is not same, after reading the packet data from the packet data storage block(5) and emitting to the serial communication line, and the output counter is augmented by receiving the packet emit signal(S6,S7).
Abstract translation: 在微处理器部分（10）（S1，S2）实现在控制在分组交换之前的输入/输出的过程中的初始状态下的输入/输出计数器的初始化。 在从分组交换主控制单元（1）接收到数据交换开始信号的情况下，关于数据存储块的输入/输出计数器增加（S3，S4）。 在输入/输出的处理过程中，表示存储在数据存储块的数据量的输入计数器的值和表示从数据存储块读取并在排队状态发出的数据量的输出计数器的值 在从分组数据存储块（5）读取分组数据并发送到串行通信线路之后，下一个分组交换不相同，并且通过接收分组发送信号来增加输出计数器（S6，S7）。
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Patent Agency Ranking
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公开(公告)号：KR1019950022459A
公开(公告)日：1995-07-28
申请号：KR1019930027113
申请日：1993-12-09
Applicant: 한국전자통신연구원
Abstract: 본 발명의 목적은 제어국내의 각 서브시스템과 기지국에서 생성된 패킷데이타의 목적지주소를 해석하여 해당 서브시스템의 접속부로 라우팅시키는 패킷 라우팅 방법과 장치를 제공하는데 있으며, 상기 목적을 달성하기 위하여 본 발명에 따른 패킷교환 처리장치는 다수의 패킷 라우터 접속장치(10)와, 버스제어장치(11)와, 패킷버스수단(12)을 구비하는데, 패킷라우터 접속장치는 패킷버스 모듈과 패킷데이타를 송수신하는데 필요한 송신부와 수신부, 제어국내의 각 서브시스템과 접속되는 패킷데이타 처리부로 이루어지며, 버스제어장치는 버스제어신호 발생부와 버스상태 관리부, BSM(Base Station Management)과 접속되는 직렬통신 접속부로 이루어지며, 본 발명에 따른 패킷 교환 처리방법은 순차적으로 각 패킷 라우터 접속장치에 버스 사용권을 할당하고 킷라우터 접속장치에서 패킷 데이타의 지정 어드레스를 해석하여 패킷 라우터 내의 채널 노드 번호(물리적 번호)를 부가시키고 이를 이용하여 패킷 데이타를 교환하는 처리절차를 구비한다.
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公开(公告)号：KR1019920009452B1
公开(公告)日：1992-10-16
申请号：KR1019900021868
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F13/38
Abstract: The circuit is for transmitting 64 bit data using 32 bit microprocessor to improve the efficiency of buses and the speed of operation. It includes a 32-bit microprocessor (1) for transmitting and receiving data by 32 bits to and from a data bus (DATA BUS) through a bus (2), a control register (3) for generating a 64 bit signal (64TR) according to the 1 bit signal from the the microprocessor (1), an address decoder (4), a local memory controller (5) for generating data acknowledge signal (LMDTACK), and local memory section (6) composed of two banks (Bank0,Bank1).
Abstract translation: 该电路用于使用32位微处理器传输64位数据，以提高总线的效率和运行速度。 它包括一个32位微处理器（1），用于通过总线（2）向数据总线（DATA BUS）发送和从数据总线（DATA BUS）发送和接收数据，用于产生64位信号（64TR）的控制寄存器（3） 根据来自微处理器（1）的1位信号，地址解码器（4），用于产生数据确认信号（LMDTACK）的本地存储器控制器（5）和由两个存储体组成的本地存储器部分（6） ，Bank1的）。
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公开(公告)号：KR100129147B1
公开(公告)日：1998-04-08
申请号：KR1019940036346
申请日：1994-12-23
Applicant: 한국전자통신연구원
IPC: H04L7/033
Abstract: Disclosed is a synchronized information transmitting method for digital mobile communication network including a transmittance delay time measuring step which initializes a synchronized transmittance system of a base station and a control station and measures a transmittance delay time between the base station and the control station, a clock phase coincidence step which coincides the phase of a predetermined clock in the base station with the clock of the control station by using the measured transmittance delay time, synchronized information transmitting step which transmits a synchronized information informing the generation of a reference clock(1PPS) through a predetermined time slot, and a reference clock regenerating step which synchronizes the reference clock(1PPS) in the base station according to the transmitted synchronized information. Thus, the trunk using efficiency between the base station and the control station in a digital mobile communication system is improved.
Abstract translation: 公开了一种用于数字移动通信网络的同步信息发送方法，包括：透射延迟时间测量步骤，其初始化基站和控制站的同步透射系统，并测量基站与控制站之间的透射延迟时间;时钟 通过使用测量的透射延迟时间将基站中的预定时钟的相位与控制站的时钟相符合的相位一致步骤，同步信息发送步骤，其通知通知生成参考时钟（1PPS）的同步信息，通过 以及基准时钟再生步骤，用于根据发送的同步信息同步基站中的参考时钟（1PPS）。 因此，提高了数字移动通信系统中基站与控制站之间的使用效率的干线。
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