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公开(公告)号：KR100536140B1
公开(公告)日：2005-12-14
申请号：KR1020020074015
申请日：2002-11-26
Applicant: 한국전자통신연구원
IPC: H01L21/205
Abstract: 본 발명은 반도체 소자의 제조 장치 및 이를 이용한 반도체 소자의 제조 방법에 관한 것으로, 낮은 온도에서 신뢰성이 높은 절연막을 효과적으로 형성 할 수 있는 반도체 소자의 제조 장치 및 이를 이용한 반도체 소자의 제조 방법을 제공한다.
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公开(公告)号：KR1020050066968A
公开(公告)日：2005-06-30
申请号：KR1020040069589
申请日：2004-09-01
Applicant: 한국전자통신연구원
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/785 , H01L21/76205 , H01L21/7624 , H01L29/42312 , H01L29/4232 , H01L29/7831
Abstract: 본 발명은 다중 게이트 모스(MOS) 트랜지스터 및 그 제조 방법에 관한 것으로, SOI(Silicon-On Insulator) 기판을 이용하여 2개의 실리콘 핀(fin)이 수직으로 적층된 구조를 형성하고, 상부 실리콘 핀의 4측면과 하부 실리콘 핀의 3측면을 채널로 이용함으로써 채널 폭이 증가되어 소자의 전류구동력이 향상되고, 공정의 최적화 및 안정화를 통해 저전력 및 고성능의 나노급 반도체 집적회로(IC) 및 고집적 메모리 집적회로(IC)를 제작할 수 있다.
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公开(公告)号：KR1020040032376A
公开(公告)日：2004-04-17
申请号：KR1020020061487
申请日：2002-10-09
Applicant: 한국전자통신연구원
IPC: G06F13/38
CPC classification number: G06F13/4217 , Y02D10/14 , Y02D10/151
Abstract: PURPOSE: A data bus system for a microcontroller is provided to increase an operation speed and reduce power consumption by reducing load capacitance of a data bus forming the data bus system. CONSTITUTION: An external access bus(204) is used by the data out from a CPU(214) and the data entering an I/O(Input/Output)(212) or an internal memory(216) from the outside. An internal access bus(202) is used by the data entering the CPU, the data out from the I/O or the internal memory, and the data out from or entering a peripheral circuit(218). An internal memory test bus(206) is used by the data out through the I/O. The external and the internal access bus are connected with each other through a latch structure(208).
Abstract translation: 目的：提供微控制器的数据总线系统，通过减少形成数据总线系统的数据总线的负载电容来提高运行速度并降低功耗。 构成：外部访问总线（204）由CPU（214）输出的数据和从外部进入I / O（输入/输出）（212）或内部存储器（216）的数据）使用。 内部访问总线（202）由进入CPU的数据，来自I / O或内部存储器的数据以及从外围电路（218）输出或进入外围电路（218）的数据使用。 内部存储器测试总线（206）由数据通过I / O使用。 外部和内部访问总线通过锁存结构（208）彼此连接。
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公开(公告)号：KR100422393B1
公开(公告)日：2004-03-11
申请号：KR1020020002695
申请日：2002-01-17
Applicant: 한국전자통신연구원
IPC: H01L29/78
CPC classification number: H01L29/0634 , H01L29/7835
Abstract: The present invention provides an EDMOS (extended drain MOS) device having a lattice type drift region and a method of manufacturing the same. In the case of n channel EDMOS(nEDMOS), the drift region has a lattice structure in which an n lattice having a high concentration and a p lattice having a low concentration are alternately arranged. As a drain voltage is applied, a depletion layer is abruptly extended by a pn junction of the n lattice and the p lattice, so that the entire drift region is easily depleted. Therefore, a breakdown voltage of the device is increased, and an on resistance of the device is decreased due to the n lattice with high concentration.
Abstract translation: 本发明提供具有晶格型漂移区的EDMOS（扩展漏极MOS）器件及其制造方法。 在n沟道EDMOS（nEDMOS）的情况下，漂移区具有其中具有高浓度的n晶格和具有低浓度的p晶格交替排列的晶格结构。 当施加漏极电压时，耗尽层由n晶格和p晶格的pn结突然延伸，使得整个漂移区容易耗尽。 因此，器件的击穿电压增加，并且由于高浓度的n晶格，器件的导通电阻降低。
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公开(公告)号：KR100418435B1
公开(公告)日：2004-02-14
申请号：KR1020010085165
申请日：2001-12-26
Applicant: 한국전자통신연구원
IPC: H01L21/76
CPC classification number: H01L27/1203 , H01L21/84
Abstract: The present invention relates to a method of fabricating a high-voltage high-power integrated circuit device using a substrate of a SOI structure in which an insulating film and a silicon layer are sequentially stacked on a silicon substrate. The method comprising the steps of sequentially forming an oxide film and a photoresist film on the silicon layer and then performing a photolithography process using a trench mask to pattern the photoresist film; patterning the oxide film using the patterned photoresist film as a mask and then removing the photoresist film remained after the patterning; etching the silicon layer using the patterned oxide film as a mask until the insulating film is exposed to form a trench; forming a nitride film on the entire surface including the trench, performing an annealing process and depositing polysilicon on the entire surface so that the trench is buried; and sequentially removing the polysilicon and the nitride film until the silicon layer is exposed to flatten the surface, thus forming a device isolating film for electrical isolation between devices within the trench. Therefore, the present invention can effectively reduce the isolation area of the trench between the high-voltage high-power device and the logic CMOS device and can easily control the concentration of a deep well.
Abstract translation: 本发明涉及一种使用SOI结构的衬底制造高压大功率集成电路器件的方法，其中绝缘膜和硅层依次堆叠在硅衬底上。 该方法包括以下步骤：在硅层上顺序形成氧化膜和光致抗蚀剂膜，然后使用沟槽掩模执行光刻工艺以图案化光致抗蚀剂膜; 使用图案化的光致抗蚀剂膜作为掩模来图案化氧化物膜，然后去除图案化之后残留的光致抗蚀剂膜; 使用图案化的氧化物膜作为掩模来蚀刻硅层，直到绝缘膜被暴露以形成沟槽; 在包括沟槽的整个表面上形成氮化物膜，执行退火工艺并且在整个表面上沉积多晶硅以便埋入沟槽; 并依次去除多晶硅和氮化物膜直到硅层暴露以使表面变平，从而形成用于沟槽内器件之间的电隔离的器件隔离膜。 因此，本发明可以有效地减少高压大功率器件与逻辑CMOS器件之间的沟槽的隔离区域，并且可以容易地控制深阱的浓度。
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Patent Agency Ranking
公开(公告)号：KR100403053B1
公开(公告)日：2003-10-23
申请号：KR1020010073392
申请日：2001-11-23
Applicant: 한국전자통신연구원
IPC: H01L27/06
Abstract: PURPOSE: A method for fabricating a Bipolar-CMOS-DMOS(BCD) device is provided to fabricate a BCD device that has voltage tolerance of 20-30 volt and 60-90 volt and gate oxide layers of different thicknesses by using a CMOS device process of a submicron class. CONSTITUTION: Only a drift region is formed under a drain region of a lateral double diffused MOS(LDMOS) device of 20-30 volt class while a drift region is formed under a drain region of 60-90 volt class so that a well region is formed to improve voltage tolerance and an on-resistance characteristic. A gate oxide layer of an nLDMOS device is made thin while a gate oxide layer of a pLDMOS device is made thick so that a gate apply voltage is increased to improve driving capability. A device occupying area is reduced by isolating devices while using a trench. A drift region of a DMOS device is formed to simplify a process by using a mask for forming the base of a bipolar device.
Abstract translation: 目的：提供一种用于制造双极-CMOS-DMOS（BCD）器件的方法，以通过使用CMOS器件工艺制造具有20-30伏和60-90伏的电压容差的BCD器件和不同厚度的栅氧化层 亚微米级的。 构成：在20-30伏特级别的横向双扩散MOS（LDMOS）器件的漏极区域下方仅形成漂移区域，而在60-90伏特的漏极区域下方形成漂移区域，使得阱区域 形成以改善电压容限和导通电阻特性。 使nLDMOS器件的栅极氧化层变薄，同时使pLDMOS器件的栅极氧化层变厚，从而提高栅极施加电压以提高驱动能力。 在使用沟槽时，通过隔离设备来减少设备占用面积。 通过使用用于形成双极器件的基极的掩模来形成DMOS器件的漂移区以简化工艺。
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公开(公告)号：KR1020030062489A
公开(公告)日：2003-07-28
申请号：KR1020020002695
申请日：2002-01-17
Applicant: 한국전자통신연구원
IPC: H01L29/78
CPC classification number: H01L29/0634 , H01L29/7835
Abstract: PURPOSE: An extended drain metal oxide semiconductor(EDMOS) device with the structure of lattice type drift region is provided to simultaneously obtain a high breakdown voltage and low on-resistance by making an np junction composed of a high density n lattice and a low density p lattice. CONSTITUTION: A well region(204) is formed in a predetermined region on a silicon substrate(201). A lattice-type drift region in which the first lattice and the second lattice are repeatedly arranged in every direction while contacting each other is formed in a predetermined region of the well region. A field oxide layer is formed in a predetermined portion of the well region or in predetermined portions of the well region and the drift region. A drain region(213) is formed in a predetermined region inside the drift region. A diffusion region is formed under the drain region. A source region(212) and a source contact region(214) are formed in a predetermined region of the well region. A gate electrode is formed in a predetermined region on the well region by interposing a gate insulation layer. A source electrode(216) is connected to the source region and the source contact region. A drain electrode(217) is connected to the drain region.
Abstract translation: 目的：提供具有晶格型漂移区结构的延伸漏极金属氧化物半导体（EDMOS）器件，通过使np结构成高密度n格和低密度，同时获得高击穿电压和低导通电阻 p格。 构成：在硅衬底（201）上的预定区域中形成阱区（204）。 在阱区域的预定区域中形成格子型漂移区域，其中第一晶格和第二晶格在彼此接触的情况下沿每个方向重复布置。 在阱区域的预定部分或阱区域和漂移区域的预定部分中形成场氧化物层。 漏极区域（213）形成在漂移区域内的预定区域中。 在漏极区域下方形成扩散区域。 源区域（212）和源极接触区域（214）形成在阱区域的预定区域中。 通过设置栅极绝缘层，在阱区的预定区域中形成栅电极。 源极（216）连接到源区和源极接触区。 漏电极（217）连接到漏区。
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公开(公告)号：KR1020030042654A
公开(公告)日：2003-06-02
申请号：KR1020010073392
申请日：2001-11-23
Applicant: 한국전자통신연구원
IPC: H01L27/06
Abstract: PURPOSE: A method for fabricating a Bipolar-CMOS-DMOS(BCD) device is provided to fabricate a BCD device that has voltage tolerance of 20-30 volt and 60-90 volt and gate oxide layers of different thicknesses by using a CMOS device process of a submicron class. CONSTITUTION: Only a drift region is formed under a drain region of a lateral double diffused MOS(LDMOS) device of 20-30 volt class while a drift region is formed under a drain region of 60-90 volt class so that a well region is formed to improve voltage tolerance and an on-resistance characteristic. A gate oxide layer of an nLDMOS device is made thin while a gate oxide layer of a pLDMOS device is made thick so that a gate apply voltage is increased to improve driving capability. A device occupying area is reduced by isolating devices while using a trench. A drift region of a DMOS device is formed to simplify a process by using a mask for forming the base of a bipolar device.
Abstract translation: 目的：提供一种用于制造双极CMOS-DMOS（BCD）器件的方法，以通过使用CMOS器件工艺来制造电压容差为20-30伏和60-90伏特的不同厚度的栅极氧化物层的BCD器件 的亚微米级。 构成：在20-30伏等级的横向双扩散MOS（LDMOS）器件的漏极区域下方仅形成漂移区域，而在60-90伏特级别的漏极区域形成漂移区域，使得阱区域为 形成以提高耐压性和导通电阻特性。 使nLDMOS器件的栅极氧化层变薄，同时使pLDMOS器件的栅极氧化物层变厚，从而增加栅极施加电压以改善驱动能力。 使用沟槽时，通过隔离装置来减少装置占用面积。 形成DMOS器件的漂移区域，以通过使用用于形成双极器件的基极的掩模来简化工艺。
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公开(公告)号：KR100596508B1
公开(公告)日：2006-07-05
申请号：KR1020030097071
申请日：2003-12-26
Applicant: 한국전자통신연구원
IPC: H01L27/092 , H01L21/8228
Abstract: 본 발명은 실리콘 기판과, 상기 실리콘 기판상에 형성된 Fin 채널, 게이트 절연막, 게이트 및 소스/드레인 전극을 포함하는 FinFET 및 FinFET의 Fin채널 제조방법에 관한 것으로서, 상기 Fin 채널은, 상기 실리콘 기판상에 형성되는 버퍼층인 경사 SiGe층상에 형성되며, 상기 경사 SiGe층 상부에 에피택셜 성장되며 적어도 일영역에 패터닝된 Fin이 구비된 이완된 SiGe층, 및 상기 이완된 SiGe층상에 적어도 상기 Fin상에 형성되는 스트레인드 실리콘층을 포함하여 구성되거나, 상기 실리콘 기판의 적어도 일영역에 패터닝된 실리콘 Fin, 상기 실리콘 Fin 상에 에피택셜 성장된 스트레인드 SiGe층, 및 상기 스트레인드 SiGe층 상에 에피택셜 실리콘층을 포함하여 구성되도록 한다. 이러한 구성을 통해서, 종래의 실리콘 FinFET 보다 소자의 성능을 크게 향상시킬 수 있다.
나노, Fin, MOSFET, FinFET, 스트레인드 Si, 스트레인드 SiGe, 게이트 절연막-
公开(公告)号：KR100541975B1
公开(公告)日：2006-01-10
申请号：KR1020030096035
申请日：2003-12-24
Applicant: 한국전자통신연구원
IPC: G09G3/30
CPC classification number: G09G3/30 , G09G2310/027 , G09G2320/0276
Abstract: 본 발명은 디지털 신호를 아날로그 신호로 변환하고 이 변환과정에서 동시에 램프 신호를 생성하는 디지털-아날로그 변환/램프 회로를 구비하는 능동 구동형 EL의 소스 구동회로를 제공한다. 이를 통해 온도나 문턱전압 변동에 무관하고 종래의 램프 회로를 사용하지 않을 수 있어 고집적도가 가능하도록 할 수 있다.
능동, 무기 EL, 소스 구동회로
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