公开(公告)号：WO2002080181A2

公开(公告)日：2002-10-10

申请号：PCT/US2001/043543

申请日：2001-11-14

Applicant: ADVANCED MICRO DEVICES, INC. ,  FUJITSU LIMITED

Inventor： BAUTISTA, Edward, V., Jr. ,  KURIHARA, Kazuhiro ,  PAN, Feng ,  LEE, Weng, Fook ,  SUNKAVALLI, Ravi ,  HAMILTON, Darlene

IPC: G11C16/00

CPC classification number: G11C16/3445 ,  G11C16/16 ,  G11C16/344

Abstract: A system (10a) is provided for reducing band-to-band tunneling current during flash memory erase operations. The system (10a) includes an I/O memory sector (20) divided into (N) subsectors, N being an integer, and a drain pump (40) to generate power for associated erase operations within the N subsectors. An erase sequencing subsystem (60) generates N pulses to enable the erase operations within each of the N subsectors in order to reduce band-to-band tunneling current provided by the drain pump (40).

Abstract translation: 提供了一种系统（10a），用于在闪速存储器擦除操作期间减少带内隧穿电流。 系统（10a）包括划分为（N）个子部分的N个整数的I / O存储器扇区（20）和用于在N个子部门内产生用于相关联的擦除操作的功率的排水泵（40）。 擦除排序子系统（60）产生N个脉冲，以便能够在N个子部门的每一个内进行擦除操作，以便减少由排水泵（40）提供的带间隧穿电流。

公开(公告)号：WO2003001601A2

公开(公告)日：2003-01-03

申请号：PCT/US2001/048825

申请日：2001-12-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RAMSBEY, Mark, T. ,  DERHACOBIAN, Narbeh ,  WANG, Janet ,  HUI, Angela ,  PHAM, Tuan ,  SUNKAVALLI, Ravi ,  RANDOLPH, Mark

IPC: H01L27/115

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11573

Abstract: One aspect of the present invention relates to a method of forming spacers (56) in a SONOS type nonvolatile semiconductor memory device, involving providing a substrate (40) having a core region (42) and periphery region (44), the core region (42) containing SONOS type memory cells (48) and the periphery region (44) containing gate transistors (50); implanting a first implant into the core region (42) and a first implant into the perifery region (44) of the substrate (40); forming a spacer material (52) over the substrate (40); masking the core region (42) and forming spacers (56) adjacent the gate transistors (50) in the perifery region (44); and implanting a second implant into the perifery region (44) of the substrate (40).

Abstract translation: 本发明的一个方面涉及一种在SONOS型非易失性半导体存储器件中形成间隔物（56）的方法，包括提供具有芯区（42）和周边区（44）的基底（40），芯区（ 42），包含SONOS型存储单元（48）和包含栅极晶体管（50）的外围区域（44）; 将第一植入物植入所述芯区域（42）中并将第一植入物植入所述基底（40）的所述外围区域（44）中; 在衬底（40）上形成间隔物（52）; 掩蔽所述芯区域（42）并在所述外形区域（44）中形成与所述栅极晶体管（50）相邻的间隔物（56）。 以及将第二植入物植入到所述基底（40）的外围区域（44）中。

公开(公告)号：EP1338034A1

公开(公告)日：2003-08-27

申请号：EP01961965.9

申请日：2001-08-07

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

Inventor： RAMSBEY, Mark, T. ,  YANG, Jean, Y. ,  SHIRAIWA, Hidehiko ,  VAN BUSKIRK, Michael, A. ,  ROGERS, David, M. ,  SUNKAVALLI, Ravi ,  WANG, Janet ,  DERHACOBIAN, Narbeh ,  WU, Yider

IPC: H01L21/8246 ,  H01L27/115

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  Y10S438/954 ,  Y10S438/981

Abstract: One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric (14) over a substrate (12), the substrate (12) having a core region (16) and a periphery region (18); removing at least a portion of the charge trapping dielectric (14) in the periphery region (18); forming a gate dielectric (22) in the periphery region (18); forming buried bitlines (26) in the core region (16); and forming gates (28) in the core region (16) and the periphery region (18).

公开(公告)号：EP1175680B1

公开(公告)日：2003-02-26

申请号：EP00930412.2

申请日：2000-05-05

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SUNKAVALLI, Ravi ,  HADDAD, Sameer, S.

IPC: G11C16/16

CPC classification number: G11C16/16

Abstract: A method for erasing a flash EEPROM cell by applying a voltage differential between the control gate and the well of the memory cell. The voltage differential can be a ramped or stepped voltage applied to the control gate, a ramped or stepped voltage applied to the well, or a ramped or stepped voltage applied to the control gate and a ramped or stepped voltage applied to the well. The ramped voltages can have a constant slope or the slope can vary. The stepped voltages can be incremented equally or unequally. The voltages applied to the well or to the control gate is ramped or stepped until a selected number of memory cells verify as erased at which time the voltages applied to the well or to the control gate is clamped until the erase procedure is finished.

公开(公告)号：EP1214715A1

公开(公告)日：2002-06-19

申请号：EP00959601.6

申请日：2000-08-29

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SUNKAVALLI, Ravi

IPC: G11C16/16

CPC classification number: G11C16/14 ,  G11C16/0416 ,  G11C16/16

Abstract: Memory devices having 1-transistor flash memory cells that in one embodiment allows bit-by-bit erase and in other embodiments allows erase of a multi-bit word. The word can be 8 bits, 16 bits, 32 bits, 64 bits or any size word. The memory devices have source bitlines that are connected to the bitline driver that controls the bitlines. The bitline driver and a wordline driver controls the voltages applied to selected bitlines, source bitlines while the wordline driver controls the voltage applied to selected wordlines to allow selected memory cells to be programmed, erased, or read.

公开(公告)号：EP1338037A1

公开(公告)日：2003-08-27

申请号：EP01999006.8

申请日：2001-11-15

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

Inventor： RAMSBEY, Mark, T. ,  YANG, Jean, Y. ,  SHIRAIWA, Hidehiko ,  VAN BUSKIRK, Michael, A. ,  ROGERS, David, M. ,  SUNKAVALLI, Ravi ,  WANG, Janet ,  DERHACOBIAN, Narbeh ,  WU, Yider

IPC: H01L27/115 ,  H01L21/8246

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11573

Abstract: One aspect of the present invention relates to a non-volatile semiconductor memory device, containing a substrate (12); a charge trapping dielectric (14) over the core region of the substrate (12); a gate dielectric in the periphery region of the substrate (12); buried bitlines (26) under the charge trapping dielectric (14) in the core region; and wordlines (28) over the charge trapping dielectric (14) in the core region, wherein the core region is substantially planar. Another aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving sequentially or non-sequentially forming a charge trapping dielectric (14) over a substrate (12); removing at least a portion of the charge trapping dielectric (14) in the periphery region (18); forming a gate dielectric (22) in the periphery region (18); forming buried bitlines (26) in the core region (16); and forming gates (28) in the core region (16) and the periphery region (18).

公开(公告)号：EP1175680A1

公开(公告)日：2002-01-30

申请号：EP00930412.2

申请日：2000-05-05

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SUNKAVALLI, Ravi ,  HADDAD, Sameer, S.

IPC: G11C16/16

CPC classification number: G11C16/16

Abstract: A method for erasing a flash EEPROM cell by applying a voltage differential between the control gate and the well of the memory cell. The voltage differential can be a ramped or stepped voltage applied to the control gate, a ramped or stepped voltage applied to the well, or a ramped or stepped voltage applied to the control gate and a ramped or stepped voltage applied to the well. The ramped voltages can have a constant slope or the slope can vary. The stepped voltages can be incremented equally or unequally. The voltages applied to the well or to the control gate is ramped or stepped until a selected number of memory cells verify as erased at which time the voltages applied to the well or to the control gate is clamped until the erase procedure is finished.