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    MEMORY CELL ARRAY WITH STAGGERED LOCAL INTER-CONNECT STRUCTURE
    1.
    发明申请
    MEMORY CELL ARRAY WITH STAGGERED LOCAL INTER-CONNECT STRUCTURE 审中-公开
    存储单元阵列与局部连接结构相结合

    公开(公告)号：WO2005038810A1

    公开(公告)日：2005-04-28

    申请号：PCT/US2004/030415

    申请日：2004-09-16

    Applicant: ADVANCED MICRO DEVICES, INC. ,  RANDOLPH, Mark ,  HADDAD, Sameer ,  THURGATE, Timothy ,  FASTOW, Richard

    Inventor： RANDOLPH, Mark ,  HADDAD, Sameer ,  THURGATE, Timothy ,  FASTOW, Richard

    IPC: G11C7/18

    CPC classification number: H01L27/11568 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521

    Abstract: A memory cell array (50) comprises a two dimensional array of memory cells (52) fabricated on a semiconductor substrate (54). The memory cells (52) are arranged in a plurality of rows defining a row direction (67) and a plurality columns defining a column direction (69). Each column of memory cells (52) comprising a plurality of alternating channel regions (58) and source/drain regions (64). A conductive interconnect (72) is positioned above each source/drain region (64) and coupled to only one other source/drain region (64). The one other source/drain region (64) is in a second column that is adjacent to the column. The conductive interconnects (64) are positioned such that every other conductive interconnect (64) connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines (70) extends between adjacent columns of memory cells (52) and electrically couple to each conductive interconnect (72) that couples between the adjacent columns.

    Abstract translation: 存储单元阵列（50）包括制造在半导体衬底（54）上的存储单元（52）的二维阵列。 存储单元（52）被布置成限定行方向（67）和限定列方向（69）的多列的多行。 每列存储单元（52）包括多个交替沟道区（58）和源/漏区（64）。 导电互连（72）位于每个源/漏区（64）上方并且仅耦合到另一个源极/漏极区（64）。 另一个源极/漏极区域（64）位于与该列相邻的第二列中。 导电互连（64）被定位成使得每隔一个导电互连（64）连接到列的右侧的相邻列，并且每隔一个导电互连连接到列的左侧的相邻列。 多个源极/漏极控制线（70）在相邻列的存储器单元（52）之间延伸并且电耦合到在相邻列之间耦合的每个导电互连（72）。

    METHOD FOR REDUCING SHORT CHANNEL EFFECTS IN MEMORY CELLS AND RELATED STRUCTURE
    2.
    发明申请
    METHOD FOR REDUCING SHORT CHANNEL EFFECTS IN MEMORY CELLS AND RELATED STRUCTURE 审中-公开
    减少记忆细胞短路通道效应的方法及相关结构

    公开(公告)号：WO2004100230A2

    公开(公告)日：2004-11-18

    申请号：PCT/US2004/011354

    申请日：2004-04-13

    Applicant: ADVANCED MICRO DEVICES, INC. ,  FUJITSU LIMITED ,  FASTOW, Richard ,  HE, Yue-Song ,  MIZUTANI, Kazuhiro ,  THURGATE, Timothy

    Inventor： FASTOW, Richard ,  HE, Yue-Song ,  MIZUTANI, Kazuhiro ,  THURGATE, Timothy

    IPC: H01L21/00

    CPC classification number: H01L27/11521 ,  H01L27/115

    Abstract: According to one exemplary embodiment, a method for fabricating a floating gate memory array comprises a step of removing (404) a dielectric material from an isolation region (110) situated in a substrate (258,358) to expose a trench (128,228), where the trench (128,228) is situated between a first source region (116,216,316) and a second source region (118,218), where the trench (128,228) defines sidewalls (150,250) in the substrate (258,358,). The method further comprises implanting (406) an N type dopant in the first source region (116,216,316), the second source region (118,218,318), and the sidewalls (150,250) of the trench (128,228), where the N type dopant forms an N+ type region (252,352). The method further comprises implanting (408) a P type dopant in the first source region (116,216,316), the second source region (118,218), and the sidewalls (150,250) of the trench (128,228), where the P type dopant forms a P type region (256,356), and where the P type region (256,356) is situated underneath the N+ type region (252,352).

    Abstract translation: 根据一个示例性实施例，一种用于制造浮动栅极存储器阵列的方法包括从位于衬底（258,358）中的隔离区（110）去除（404）电介质材料以暴露沟槽（128,228）的步骤，其中 沟槽（128,228）位于第一源极区域（116,216,316）和第二源极区域（118,218）之间，其中沟槽（128,228）限定衬底（258,358）中的侧壁（150,250）。 该方法还包括在第一源区（116,216,316），第二源区（118,218,318）和沟槽（128,228）的侧壁（150,250）中注入（406）N型掺杂剂，其中N型掺杂剂形成N + 类型区域（252,352）。 该方法还包括在第一源区（116,216,316），第二源区（118,218）和沟槽（128,228）的侧壁（150,250）中注入（408）P型掺杂剂，其中P型掺杂剂形成P 类型区域（256,356），并且其中P型区域（256,356）位于N +型区域（252,352）下方。

    CHARGE INJECTION
    3.
    发明申请
    CHARGE INJECTION 审中-公开
    充电注射

    公开(公告)号：WO2003063167A2

    公开(公告)日：2003-07-31

    申请号：PCT/US2002/040775

    申请日：2002-12-17

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： HAMILTON, Darlene ,  THURGATE, Timothy ,  WANG, Janet, S. Y. ,  HAN, Michael, K. ,  DERHACOBIAN, Narbeh

    IPC: G11C

    CPC classification number: G11C16/3409 ,  G11C11/5657 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3404 ,  G11C16/3436 ,  G11C16/3445

    Abstract: A system and methodology is provided for programming first bit (CO, C2, C4, C6) and second bit (C1, C3, C5, C7) of a memory array (68) of dual bit memory cells (10, 82, 84, 86, 88) at a substantially high delta VT. The substantially higher VT assures that the memory array (68) will maintain programmed data and erase data consistently after higher temperature stresses and/or custumer operation over substantial periods of time. At a substantially higher delta VT, programming of the first bit (C0, C2, C4, C6) of the memory cell (10, 82, 84, 86, 88) causes the second bit (C1, C3, C5, C7) to program harder and faster due to the shorter channel (8) length. Therefore, the present invention employs selected gate and drain voltages and programming pulse widths during programming of the first bit (C0, C2, C4, C6) and second bit (C1, C3, C5, C7) that assures a controlled first bit VT and slows down programming of the second bit (C1,C3, C5, C7). Furthermore, the selected programming parameters keep the programming times short without degrading charge loss.

    Abstract translation: 提供了一种系统和方法，用于对双位存储器单元（10,82,84,86）的存储器阵列（68）的第一位（CO，C2，C4，C6）和第二位（C1，C3，C5，C7） 86,88）处于基本上高的三角洲VT。 基本上较高的VT确保存储器阵列（68）将在相当长的一段时间内在更高的温度应力和/或操作者操作之后保持编程的数据并且一致地擦除数据。 在基本上较高的增量VT下，存储器单元（10,82,84,86,88）的第一位（C0，C2，C4，C6）的编程使第二位（C1，C3，C5，C7） 由于短通道（8）的长度，程序越来越快。 因此，本发明在第一位（C0，C2，C4，C6）和第二位（C1，C3，C5，C7）的编程期间采用选定的栅极和漏极电压和编程脉冲宽度，以确保受控的第一位VT和 减慢第二位（C1，C3，C5，C7）的编程速度。 此外，所选择的编程参数保持编程时间短而不降低电荷损耗。

    METHOD OF PRODUCING A LATERALLY DOPED CHANNEL
    4.
    发明申请
    METHOD OF PRODUCING A LATERALLY DOPED CHANNEL 审中-公开
    生产侧向通道的方法

    公开(公告)号：WO2004049446A1

    公开(公告)日：2004-06-10

    申请号：PCT/US2003/021667

    申请日：2003-07-10

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： WONG, Nga-Ching ,  THURGATE, Timothy ,  HADDAD, Sameer, S.

    IPC: H01L27/115

    CPC classification number: H01L27/11521 ,  H01L21/26586 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/1045 ,  H01L29/66825 ,  H01L29/66833

    Abstract: A lateral doped channel, particularly in a MOSFET of a semiconductor memory cell. A first doping material (210) is implanted substantially vertically into a region (220) adjacent to a gate structure. A diffusion process diffuses the first doping material into a channel region beneath the gate structure. A second doping material (240) is implanted substantially vertically into the region (220) adjacent to a gate structure. The second implantation forms source/drain regions (250) and may terminate the channel region. The channel region thus comprises a laterally non-uniform doping profile which beneficially mitigates the short channel effect and is highly advantageous as compensation for manufacturing process variations in channel length. The memory cell may be a floating gate type or a nitride type (SONOS) non-volatile memory.

    Abstract translation: 横向掺杂沟道，特别是在半导体存储单元的MOSFET中。 基本垂直地将第一掺杂材料（210）注入到与栅极结构相邻的区域（220）中。 扩散过程将第一掺杂材料扩散到栅极结构下方的沟道区域中。 基本上垂直地将第二掺杂材料（240）注入到与栅极结构相邻的区域（220）中。 第二注入形成源/漏区（250）并且可以终止沟道区。 因此，通道区域包括横向不均匀的掺杂分布，其有利地减轻了短沟道效应，并且作为对通道长度的制造工艺变化的补偿是非常有利的。 存储单元可以是浮栅型或氮化物型（SONOS）非易失性存储器。

    MEMORY CELL ARRAY WITH STAGGERED LOCAL INTER-CONNECT STRUCTURE
    6.
    发明授权
    MEMORY CELL ARRAY WITH STAGGERED LOCAL INTER-CONNECT STRUCTURE 有权
    存储单元阵列与毕业于本地连接结构

    公开(公告)号：EP1673781B1

    公开(公告)日：2007-07-25

    申请号：EP04784309.9

    申请日：2004-09-16

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： RANDOLPH, Mark ,  HADDAD, Sameer ,  THURGATE, Timothy ,  FASTOW, Richard

    IPC: G11C7/18 ,  G11C16/04

    CPC classification number: H01L27/11568 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521

    Abstract: A memory cell array (50) comprises a two dimensional array of memory cells (52) fabricated on a semiconductor substrate (54). The memory cells (52) are arranged in a plurality of rows defining a row direction (67) and a plurality columns defining a column direction (69). Each column of memory cells (52) comprising a plurality of alternating channel regions (58) and source/drain regions (64). A conductive interconnect (72) is positioned above each source/drain region (64) and coupled to only one other source/drain region (64). The one other source/drain region (64) is in a second column that is adjacent to the column. The conductive interconnects (64) are positioned such that every other conductive interconnect (64) connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines (70) extends between adjacent columns of memory cells (52) and electrically couple to each conductive interconnect (72) that couples between the adjacent columns.

    MEMORY CELL ARRAY WITH STAGGERED LOCAL INTER-CONNECT STRUCTURE
    8.
    发明公开
    MEMORY CELL ARRAY WITH STAGGERED LOCAL INTER-CONNECT STRUCTURE 有权
    存储单元阵列与毕业于本地连接结构

    公开(公告)号：EP1673781A1

    公开(公告)日：2006-06-28

    申请号：EP04784309.9

    申请日：2004-09-16

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： RANDOLPH, Mark ,  HADDAD, Sameer ,  THURGATE, Timothy ,  FASTOW, Richard

    IPC: G11C7/18 ,  G11C16/04

    CPC classification number: H01L27/11568 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521

    Abstract: A memory cell array (50) comprises a two dimensional array of memory cells (52) fabricated on a semiconductor substrate (54). The memory cells (52) are arranged in a plurality of rows defining a row direction (67) and a plurality columns defining a column direction (69). Each column of memory cells (52) comprising a plurality of alternating channel regions (58) and source/drain regions (64). A conductive interconnect (72) is positioned above each source/drain region (64) and coupled to only one other source/drain region (64). The one other source/drain region (64) is in a second column that is adjacent to the column. The conductive interconnects (64) are positioned such that every other conductive interconnect (64) connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines (70) extends between adjacent columns of memory cells (52) and electrically couple to each conductive interconnect (72) that couples between the adjacent columns.

    NON-VOLATILE MEMORY WITH SOURCE SIDE BORON IMPLANTATION
    10.
    发明公开
    NON-VOLATILE MEMORY WITH SOURCE SIDE BORON IMPLANTATION 审中-公开
    与电源侧硼注入FESTIVAL MEMORY

    公开(公告)号：EP1356505A1

    公开(公告)日：2003-10-29

    申请号：EP01957475.5

    申请日：2001-08-06

    Applicant: ADVANCED MICRO DEVICES INC.

    Inventor： HADDAD, Sameer ,  RANDOLPH, Mark, W. ,  HE, Yue-Song ,  THURGATE, Timothy ,  CHANG, Chi ,  WONG, Ngaching

    IPC: H01L21/336 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L29/66825 ,  H01L29/66833

    Abstract: One aspect of the present invention relates to a method of making a flash memory cell (32), involving providing a substrate (30) having a flash memory cell (32) thereon; forming a self-aligned source mask (48) over the substrate, the self aligned source mask (48) having openings (50) corresponding to source lines; implanting a source dopant of a first type in the substrate through the openings (50) in the self-aligned source mask (48) corresponding to source lines (52); removing the self-aligned source mask (48) from the substrate (30); forming a MDD mask (54) over the substrate (30), the MDD mask (54) covering the source lines (52) and having openings (56) corresponding to drain lines; and implanting a medium dosage drain implant of a second type to form a drain region (58) in the substrate (30) adjacent the flash memory cell (32).

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