公开(公告)号：JPH0595088A

公开(公告)日：1993-04-16

申请号：JP5747192

申请日：1992-02-10

Applicant: AGENCY IND SCIENCE TECHN

Inventor： HAYASHI YUTAKA ,  SUZUKI HIDEKAZU ,  SEKIKAWA TOSHIHIRO ,  NAGAI KIYOKO ,  KAWANAMI HITOSHI

IPC: H01L21/20 ,  H01L21/203 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: PURPOSE:To provide a semiconductor device using a semiconductor single crystal layer as an insulating substance and moreover providing a field effect transistor having an electron channel and a hole channel. CONSTITUTION:An insulated gate type field effect transistor is formed by providing a first single crystal silicon layer 10, a single crystal AIP layer 20 as an insulated gate substance which is provided on the single silicon layer 10 and has a barrier of 0.24eV or higher under the room temperature for both electron and hole of the first single crystal silicon layer 10 and a gate electrode 32, a source 12 and a drain 13 formed on the single crystal AIP layer 20.

公开(公告)号：JPS63146470A

公开(公告)日：1988-06-18

申请号：JP27689987

申请日：1987-10-30

Applicant: AGENCY IND SCIENCE TECHN

Inventor： SUZUKI HIDEKAZU ,  SEKIKAWA TOSHIHIRO ,  KAWANAMI HITOSHI ,  NAGAI KIYOKO

IPC: H01L21/8247 ,  H01L27/00 ,  H01L29/267 ,  H01L29/788 ,  H01L29/792 ,  H01L29/80

Abstract: PURPOSE:To realize high density integration, by applying a GaP crystal layer to an insulating gate material, and using an Si crystal layer as a semiconductor crystal floating gate. CONSTITUTION:ON a first silicon crystal layer 10, a single crystal GaP layer 20 is formed, and a floating gate 23 composed of single crystal silicon is formed in the GaP layer 20. The forbidden bandwidth of the GaP layer 20 is larger as compared with that of single crystal silicon, and lattice deffect does not generate. The lattice constants are very approximate to those of single crystal silicon. Consequently, many layers of memory elements composed of a second single crystal silicon layer 30, the single crystal GaP layer 20, and a floating gate, etc., can be formed on the nonvolatile memory element constituted in the above mentioned manner.

公开(公告)号：JP2000150792A

公开(公告)日：2000-05-30

申请号：JP32009298

申请日：1998-11-11

Applicant: AGENCY IND SCIENCE TECHN

Inventor： ARAI KAZUO ,  YOSHIDA SADAJI ,  OKUMURA HAJIME ,  NAGAI KIYOKO ,  SEKIKAWA TOSHIHIRO ,  FUKUDA KENJI

IPC: H01L27/04 ,  H01L21/318 ,  H01L21/324 ,  H01L21/822 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To improve the electric characteristic of a semiconductor device so that the device may have a high dielectric breakdown voltage and a low interfacial level density. SOLUTION: In a semiconductor device provided with a metallic layer formed on a semiconductor substrate containing silicon carbide in at least its uppermost layer through an insulator, the insulator is constituted by laminating an oxide film and/or a nitride film upon the lowermost aluminum nitride layer. In addition, after the insulator is formed on the semiconductor substrate or the metallic layer is formed on the insulator, hydrogen annealing or hydrogen plasma irradiation is performed.

公开(公告)号：JPS6252979A

公开(公告)日：1987-03-07

申请号：JP19238585

申请日：1985-08-31

Applicant: AGENCY IND SCIENCE TECHN

Inventor： HAYASHI YUTAKA ,  KAWANAMI HITOSHI ,  NAGAI KIYOKO

IPC: H01L31/10 ,  H01L33/30 ,  H01L33/34 ,  H01L33/36

Abstract: PURPOSE:To provide an energy barrier against minority carries even if a semiconductor region with a narrow energy gap is brought into contact from the outside by a method wherein the first and the second semiconductor regions are formed with the combina tion of materials with which a barrier,blocking carriers of the conductivity type oppo site to the first conductivity type, is formed in a junction plane between the second semiconductor region and the first semiconductor region. CONSTITUTION:An N-type region 10, doped with phosphorus atoms with surface concen tration of 10 cm , is formed in the surface of a P-type 3OMEGAcm (100) face silicon sub strate by a selective diffusion technology. An SiO2 layer 12 is formed on the substrate surface and an aperture is drilled on the surface of the region 10. A single crystal N-type GaP layer 20 and a single crystal P-type GaP layer 21 are made to grow in the aperture to the thickness of 3mum by a molecular beam epitaxial apparatus. During the epitaxial growth, Si is doped to form the N-type layer 20 and B6 is doped to form the P-type layer 21 so as to have carrier concentration of 10 cm . After that,the island shape GaP is left by selective etching and ZnO is deposited and thermal diffusion is carried out. With this constitution, the light emitting center in the GaP is introduced.

公开(公告)号：JP2000252461A

公开(公告)日：2000-09-14

申请号：JP5239699

申请日：1999-03-01

Applicant: AGENCY IND SCIENCE TECHN ,  NEW ENERGY & IND TECHNOLOGY DE

Inventor： ARAI KAZUO ,  YOSHIDA SADAJI ,  NAGAI KIYOKO ,  SEKIKAWA TOSHIHIRO ,  FUKUDA KENJI

IPC: H01L29/78 ,  H01L21/04 ,  H01L21/316 ,  H01L21/324

Abstract: PROBLEM TO BE SOLVED: To provide a MOS capacitor of interface level density by forming at least one layer of oxide film and nitride film as a gate insulating film on a semiconductor substrate comprising a silicon carbide on the top layer before annealing in the atmosphere containing hydrogen at a temperature in specified range. SOLUTION: On a semiconductor substrate comprising a silicon carbide(SiC) on its top, at least one layer of gate insulating film comprising oxide film and nitride film is formed for annealing in the atmosphere containing hydrogen at 600-1600 deg.C thereafter, so that dangling bond of carbon or silicon present at an insulating film/silicon carbide interface is terminated, thus reducing an interface level density for better interface. Al is used for a gate electrode and ohmic contact to produce a MOS capacitor, eventually. Thus, an insulating film/silicon carbide interface sufficiently resistant for actual use is provided.

公开(公告)号：JPS6284554A

公开(公告)日：1987-04-18

申请号：JP22410285

申请日：1985-10-08

Applicant: AGENCY IND SCIENCE TECHN

Inventor： HAYASHI YUTAKA ,  ISHII KENICHI ,  KAWANAMI HITOSHI ,  NAGAI KIYOKO ,  ISHIHARA SEIICHI

IPC: H01L21/822 ,  H01L27/04 ,  H01L27/14 ,  H01L27/15

Abstract: PURPOSE:To manufacture an integrated circuit, in which mutual wirings among elements are formed without crossing large stepped sections and electronic elements and optical elements are integrated in a monolithic manner with high density, by shaping an element-forming region section in a semiconductor layer as an upper section in a single crystal region and forming other field sections by a polycrystal or amorphous. CONSTITUTION:A second insulating film 11 is shaped onto a semiconductor crystal substrate 10, and an opening 11a is formed into the second insulating film 11. 100 represents an upper semiconductor thin-film, a section 101 being in contact with the semiconductor crystal substrate 10 through the upper opening 11a is formed in a single crystal region, the semiconductor thin-film 100 sections adjacent to the single crystal region 101 are shaped in polycrystalline regions 102, and a section separate from the single crystal region 101 is formed in an amorphous region 103. A conductive thin-film 120 is arranged to the single crystal region 101 by forming the conductive thin-film 120 through an insulating film 121 or while being directly brought into contact with the semiconductor thin-film 100.