公开(公告)号：JP2000150792A

公开(公告)日：2000-05-30

申请号：JP32009298

申请日：1998-11-11

Applicant: AGENCY IND SCIENCE TECHN

Inventor： ARAI KAZUO ,  YOSHIDA SADAJI ,  OKUMURA HAJIME ,  NAGAI KIYOKO ,  SEKIKAWA TOSHIHIRO ,  FUKUDA KENJI

IPC: H01L27/04 ,  H01L21/318 ,  H01L21/324 ,  H01L21/822 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To improve the electric characteristic of a semiconductor device so that the device may have a high dielectric breakdown voltage and a low interfacial level density. SOLUTION: In a semiconductor device provided with a metallic layer formed on a semiconductor substrate containing silicon carbide in at least its uppermost layer through an insulator, the insulator is constituted by laminating an oxide film and/or a nitride film upon the lowermost aluminum nitride layer. In addition, after the insulator is formed on the semiconductor substrate or the metallic layer is formed on the insulator, hydrogen annealing or hydrogen plasma irradiation is performed.

公开(公告)号：JPH0878495A

公开(公告)日：1996-03-22

申请号：JP20954294

申请日：1994-09-02

Applicant: AGENCY IND SCIENCE TECHN

Inventor： YUI NAOMASA ,  SEKIKAWA TOSHIHIRO

IPC: G01R31/26 ,  G01M11/00 ,  G01R31/36 ,  H01L21/66 ,  H01L31/04

Abstract: PURPOSE: To simply and rapidly detect the presence and the quantity of a carrier trap despite the omission of measuring a spectral sensitivity curve by irradiating a semiconductor P-N junction element with weak white light, and detecting the change of the spectral sensitivity characteristics of the element by measuring current-voltage characteristics. CONSTITUTION: Minority carrier trap of a semiconductor P-N junction element 5 is evaluated according to the change of the spectral sensitivity characteristics of the element 5. In such a method for evaluating the element 5, the change of the characteristics of the element 5 is detected by irradiating the element 5 of a dark state with weak white light 2, and measuring the current-voltage (Δi-V) characteristics of the element 5 by the light 2. For example, the light 2 of about 0.2mW/cm is emitted to a sample 5 via an optical chopper 3, and the DC current-voltage (I-V) and the output current-voltage (Δi-V) characteristics by the light 2 are measured.

公开(公告)号：JPH07147233A

公开(公告)日：1995-06-06

申请号：JP29369193

申请日：1993-11-24

Applicant: AGENCY IND SCIENCE TECHN ,  CITIZEN WATCH CO LTD

Inventor： SEKIKAWA TOSHIHIRO ,  ISHII KENICHI ,  AIHARA KATSUYOSHI

IPC: H01L21/20 ,  H01L21/02 ,  H01L21/336 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

Abstract: PURPOSE:To form a single crystal silicon film which is stable and has large area, on an insulating film. CONSTITUTION:In the manufacturing method of a semiconductor thin film wherein, after an insulating film 2 is formed on a single crystal silicon substrate, and a seed region 3 where the single crystal silicon substrate 1 surface is exposed by partially eliminating the insulating film 2 is formed, a semiconductor thin film is formed on the seed region 3 and the insulating film 2, a process for forming an epitaxial silicon layer from the seed region to the upper surface of the insulating film 2 by using a selective epitaxial growth method of silicon is contained. Further a process for forming an amorphous silicon film on the whole surfaces of the epitaxial silicon layer and the insulating film, and a process for converting the amorphous silicon film into a single crystal silicon film 5 by solid growth applying the epitaxial silicon layer to seed crystal by heat treatment are contained.

公开(公告)号：JPH07130656A

公开(公告)日：1995-05-19

申请号：JP30234293

申请日：1993-11-08

Applicant: AGENCY IND SCIENCE TECHN

Inventor： YUI NAOMASA ,  YAMANAKA MITSUYUKI ,  SEKIKAWA TOSHIHIRO

IPC: H01L21/205

Abstract: PURPOSE:To provide a method of growing a crystalline semiconductor thin film. CONSTITUTION:While supplying a raw gas for a semiconductor onto a light- transmitting substrate 1, the rear side of the light-transmitting substrate 1 is illuminated to form a dark and bright pattern having a regularity in the two-dimensional direction along the surface on the surface of the substrate 1, and a crystalline thin film 8 is formed on the substrate 1 by scanning the pattern 4 in the direction 7 along the surface of the substrate.

公开(公告)号：JPH06318712A

公开(公告)日：1994-11-15

申请号：JP9583394

申请日：1994-04-08

Applicant: AGENCY IND SCIENCE TECHN

Inventor： SUZUKI HIDEKAZU ,  SEKIKAWA TOSHIHIRO ,  HAYASHI YUTAKA

IPC: H01L27/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L27/12 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To provide a nonvolatile semiconductor memory element which can store a number of bits in one element and, at the same time, has a small occupying area. CONSTITUTION:A trapezoid semiconductor section 9 with a channel forming area 23 on its surface is formed on the main surface of a substrate 1 and a charge storing member 6 is provided on the surface of the section 9. In order to divide the member 6 into effective charge storing areas respectively having prescribed widths of W1, W2, and W3, a first, second, and third gate electrodes 51, 52, and 53 respectively having the corresponding widths W1, W2, and W3 are provided. At least some of the gate electrodes, for example, the first and second gate electrodes 51 and 52 are provided along the side faces of the section 9.

公开(公告)号：JPH03231471A

公开(公告)日：1991-10-15

申请号：JP2685690

申请日：1990-02-06

Applicant: AGENCY IND SCIENCE TECHN

Inventor： SEKIKAWA TOSHIHIRO ,  ISHII KENICHI ,  HAYASHI YUTAKA

IPC: H01L29/78 ,  H01L29/786

Abstract: PURPOSE:To sharply enhance the characteristic and the reliability of an IGFET whose channel has been made short by a method wherein the length of an insulator layer formed at the lower part of a drain region is specified. CONSTITUTION:At an IGFET 10, an insulator layer 17 is formed between a drain region 14 and a semiconductor region 11. The insulator layer 17 is extended toward the side of a source region 13 from the junction part of the drain region 14 and a channel region 12; it is terminated at a position which does not reach the junction part of the source region 13 and the channel region 12. Since the insulator layer is situated between the drain region 14 and the semiconductor region 11, it is limited that a depletion layer which can be generated from the drain region 14 is extended to the semiconductor region. In addition, since a structure part sandwiched between a gate region 16 and the semiconductor region 11 via the insulator layer 17 exists, also a required shielding effect is given.

公开(公告)号：JPS62179784A

公开(公告)日：1987-08-06

申请号：JP2249486

申请日：1986-02-04

Applicant: AGENCY IND SCIENCE TECHN

Inventor： SEKIKAWA TOSHIHIRO ,  HAYASHI YUTAKA

IPC: H01L49/02 ,  H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: PURPOSE:To provide high speed, small size and low power consumption in a field-effect transistor utilizing a tunnel phenomenon by forming a channel region of an insulating material having electron affinity of smaller value than a work function of the material for forming a source region. CONSTITUTION:The electron affinity of an insulator material for forming a channel region 14 is set small for a work function of the material of a source region 12. In other words, a high density N-type silicon film 17 is formed on an insulator substrate 11, a silicon oxide film 18 is formed thereon, a hole 19 is opened at a predetermined position to expose the surface of the film 17. Then, with the remaining film 18 as a mask a portion matched to the hole 18 of the film 17 is thermally nitrided to form a silicon nitride film 14 to become the channel region 14, and the regions of both sides are simultaneously specified as source and drain regions 12, 13. Thereafter, the surface of the film 14 is thermally oxidized to form a silicon oxide film 15 to become a gate insulating film, and a gate electrode 16 is formed corresponding to a predetermined pattern on the upper surface.

公开(公告)号：JP2000252461A

公开(公告)日：2000-09-14

申请号：JP5239699

申请日：1999-03-01

Applicant: AGENCY IND SCIENCE TECHN ,  NEW ENERGY & IND TECHNOLOGY DE

Inventor： ARAI KAZUO ,  YOSHIDA SADAJI ,  NAGAI KIYOKO ,  SEKIKAWA TOSHIHIRO ,  FUKUDA KENJI

IPC: H01L29/78 ,  H01L21/04 ,  H01L21/316 ,  H01L21/324

Abstract: PROBLEM TO BE SOLVED: To provide a MOS capacitor of interface level density by forming at least one layer of oxide film and nitride film as a gate insulating film on a semiconductor substrate comprising a silicon carbide on the top layer before annealing in the atmosphere containing hydrogen at a temperature in specified range. SOLUTION: On a semiconductor substrate comprising a silicon carbide(SiC) on its top, at least one layer of gate insulating film comprising oxide film and nitride film is formed for annealing in the atmosphere containing hydrogen at 600-1600 deg.C thereafter, so that dangling bond of carbon or silicon present at an insulating film/silicon carbide interface is terminated, thus reducing an interface level density for better interface. Al is used for a gate electrode and ohmic contact to produce a MOS capacitor, eventually. Thus, an insulating film/silicon carbide interface sufficiently resistant for actual use is provided.

公开(公告)号：JPS6459960A

公开(公告)日：1989-03-07

申请号：JP21750087

申请日：1987-08-31

Applicant: AGENCY IND SCIENCE TECHN

Inventor： SUZUKI HIDEKAZU ,  SEKIKAWA TOSHIHIRO ,  HAYASHI YUTAKA

IPC: H01L27/112 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/00 ,  H01L27/115 ,  H01L27/12 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To enable a nonvolatile semiconductor memory element to store many states or bits in one element by a method wherein plural channels independent of each other are selectively formed between a source and a drain or plural effective charge storage regions independent of each other are provided along a broadwise direction intersected with a lengthwise direction at right angles. CONSTITUTION:A source 21 and a drain 22 are formed on a superficial region of a semiconductor substrate 11 separating from each other at required distance. Plural electrodes (in Figure, three electrodes 51, 52, and 53) formed out of adequate conductive materials such as polycrystalline silicon, metal, silicide, or the like are formed in the range corresponding to the space between the source and the drain on a gate insulating film 8 or a charge storage component 6. Provided that the direction in which the source is in line with the drain is prescribed as a lengthwise direction (this corresponds usually to a case in which the concept such as a channel length or a channel width is made to be prescribed), these electrodes, 51, 52, and 53, are made to be separated from each other in a broadwise direction and independent of each other.

公开(公告)号：JPH1081597A

公开(公告)日：1998-03-31

申请号：JP23397596

申请日：1996-09-04

Applicant: AGENCY IND SCIENCE TECHN

Inventor： YUI NAOMASA ,  SEKIKAWA TOSHIHIRO ,  YAMANAKA MITSUYUKI ,  SAKATA ISAO

IPC: C30B29/06 ,  C23C16/50 ,  H01L21/205

Abstract: PROBLEM TO BE SOLVED: To exclude damage due to a plasma and prepare a high-quality silicon thin film by depositing the silicon thin film under specific conditions without carrying out the external heating of a substrate when performing the formation of the silicon thin film on an insulating substrate surface according to a plasma CVD (chemical vapor deposition) method. SOLUTION: A substrate 11 is arranged in a position thereof at >=150 deg.C, preferably >=100 deg.C temperature of self heating of the substrate 11 with a plasma during the film formation and separated parallel from a plane for connecting ends of one or more pairs of comb-shaped electrodes 13 for preferably producing plasmas 14 by 4 17 mm and a silicon thin film is deposited on the surface of the substrate 11 while applying a positive DC bias potential through an electroconductive thin film 11A (e.g. an Al film) formed on the back surface of the substrate 11 thereto without carrying out the external heating of the substrate 11. The DC bias potential is changed to thereby change the band gap width of the silicon thin film during the formation thereof.