公开(公告)号：JPH11150079A

公开(公告)日：1999-06-02

申请号：JP31488697

申请日：1997-11-17

Applicant: AGENCY IND SCIENCE TECHN

Inventor： ARAI KAZUO ,  YOSHIDA SADAJI ,  TAGAMI HISAO ,  TANAKA YASUNORI ,  OKUMURA HAJIME

IPC: H01J37/317 ,  H01L21/265

Abstract: PROBLEM TO BE SOLVED: To implant ions at high doping ion flux, by allowing doping ions which cause electrical activity to be pulse a for ion implantation. SOLUTION: Pulse-like ion species generated by laser application, etc., are classified and accelerated for common ion implantation source together with doping pulse ion source. Timing is adjusted between implantation temperature and ion flux as well as state control pulse flux and doping ion pulse, for optimizing. Further, a pulse ion implantation and irradiation of excited control pulse train are coupled. Further, micro implantation condition control is performed for the doping ion, allowing optimum control of a dopant in electrical activity.

公开(公告)号：JP2001102641A

公开(公告)日：2001-04-13

申请号：JP27752099

申请日：1999-09-29

Applicant: AGENCY IND SCIENCE TECHN ,  MAKITA YUNOSUKE ,  TAGAMI HISAO

Inventor： MAKITA YUNOSUKE ,  TAGAMI HISAO

IPC: H01L21/363 ,  H01L31/04 ,  H01L31/10 ,  H01L33/34 ,  H01L35/14 ,  H01L35/32 ,  H01L39/12 ,  H01M14/00 ,  H01L33/00

Abstract: PROBLEM TO BE SOLVED: To provide a method by which a β-iron silicide heterostructure for semiconductor device can be manufactured. SOLUTION: A β-iron silicide crystal heterostructure is manufactured on a substrate by conducting a chemical vapor phase transportation method by setting up and sealing a polycrystalline iron silicide material, a transporting medium, a dopant material, and a substrate material composed of calcium fluoride, silicon, or iron at the crystal growing position of the substrate.

公开(公告)号：JPS61201329A

公开(公告)日：1986-09-06

申请号：JP4226685

申请日：1985-03-04

Applicant: AGENCY IND SCIENCE TECHN

Inventor： DAITO SHIGEO ,  SAKAMOTO KOJI ,  KUROSAWA ITARU ,  TSURUSHIMA TOSHIO ,  TAGAMI HISAO

IPC: G06F7/53 ,  G06F7/508 ,  G06F7/52

Abstract: PURPOSE:To shorten a critical path by arranging an array multiplier in three dimensions and eliminating a bridge part. CONSTITUTION:Respective array multipliers AM1, AM2, AM3, and AM4 for respective operand part group areas are all arranged separately in layers #1-#4 of levels LV1-LV4 which are overlaid in the height direction and adjoin vertically and directly. No bridge is formed among paths, so a carry preserving adder CAS1 for the array multipliers in the levels LV4 and LV3 and a carry preserving adder CAS2 for the array multipliers in the levels LV2 and LV3 are arranged extremely closely to the array multiplier group and a carry look- ahead adder CLA is also arranged closely.