公开(公告)号：WO2010135097A2

公开(公告)日：2010-11-25

申请号：PCT/US2010034149

申请日：2010-05-08

Applicant: ALTERA CORP ,  HOANG TIM TRI ,  TRAN THUNGOC ,  WONG WILSON ,  SHUMARAYEV SERGEY

Inventor： HOANG TIM TRI ,  TRAN THUNGOC ,  WONG WILSON ,  SHUMARAYEV SERGEY

IPC: G06F1/10 ,  H03K19/177

CPC classification number: G06F1/10

Abstract: A circuit includes a first area, a second area, and a third area. The second area includes a locked loop circuit that generates a clock signal. The locked loop circuit receives a supply voltage that is isolated from noise generated in the first area. The third area includes multiple quads of channels and a clock line coupled to route at least one clock signal generated in the second area to the channels in each of the quads. The third area is separate from the second area in the circuit.

Abstract translation: 电路包括第一区域，第二区域和第三区域。 第二区域包括产生时钟信号的锁定环路电路。 锁定环电路接收与第一区域中产生的噪声隔离的电源电压。 第三区域包括多个通道的四通道，并且时钟线耦合以将在第二区域中产生的至少一个时钟信号路由到每个四通道中的通道。 第三个区域与电路中的第二个区域分开。

公开(公告)号：WO2012138509A3

公开(公告)日：2013-01-03

申请号：PCT/US2012030753

申请日：2012-03-27

Applicant: ALTERA CORP ,  DING WEIQI ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  HOANG TIM TRI ,  KE YANJING

Inventor： DING WEIQI ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  HOANG TIM TRI ,  KE YANJING

IPC: H04B1/04 ,  H03L7/00

CPC classification number: H03K5/1565 ,  H03K3/017 ,  H03K5/12 ,  H03M9/00

Abstract: A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.

Abstract translation: 发射机电路可操作以响应于第一周期性信号提供输出信号。 多路复用器电路可操作以在第一操作阶段期间提供作为选定信号的第二周期信号。 多路复用器电路可操作以在第二操作阶段期间将发射机电路的输出信号提供为所选择的信号。 采样器电路可操作以在第一操作阶段产生所选信号的第一采样。 采样器电路可操作以在第二操作阶段期间产生所选信号的第二采样。 占空比控制电路可操作以基于第一和第二采样来调整第一周期信号的占空比。

公开(公告)号：WO2010033436A2

公开(公告)日：2010-03-25

申请号：PCT/US2009056753

申请日：2009-09-11

Applicant: ALTERA CORP ,  HOANG TIM TRI ,  WONG WILSON ,  SHUMARAYEV SERGEY

Inventor： HOANG TIM TRI ,  WONG WILSON ,  SHUMARAYEV SERGEY

IPC: H03L7/193 ,  H03L7/087

CPC classification number: H03L7/099 ,  H03L7/18

Abstract: A circuit includes phase detection circuitry, a clock signal generation circuit, a first frequency divider, and a second frequency divider. The phase detection circuitry compares an input clock signal to a feedback signal to generate a control signal. The clock signal generation circuit generates a periodic output signal in response to the control signal. The first frequency divider divides a frequency of the periodic output signal by a first value to generate a first frequency divided signal. The second frequency divider divides the frequency of the periodic output signal by a second value to generate a second frequency divided signal. The first and the second frequency divided signals are routed to the phase detection circuitry as the feedback signal during different time intervals.

Abstract translation: 一种电路包括相位检测电路，时钟信号生成电路，第一分频器和第二分频器。 相位检测电路将输入时钟信号与反馈信号进行比较以生成控制信号。 时钟信号产生电路响应于控制信号产生周期性输出信号。 第一分频器将周期性输出信号的频率除以第一值以产生第一分频信号。 第二分频器将周期性输出信号的频率除以第二值以产生第二分频信号。 第一和第二分频信号在不同的时间间隔期间作为反馈信号被路由到相位检测电路。

公开(公告)号：AT549797T

公开(公告)日：2012-03-15

申请号：AT05778119

申请日：2005-08-02

Applicant: ALTERA CORP

Inventor： LUI HENRY Y ,  KABANI MALIK ,  PATEL RAKESH ,  HOANG TIM TRI

IPC: H03K19/177

公开(公告)号：JP2008072716A

公开(公告)日：2008-03-27

申请号：JP2007237202

申请日：2007-09-12

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： WONG WILSON ,  CHAN DORIS PO CHING ,  SHUMARAYEV SERGEY ,  MAANGAT SIMARDEEP ,  HOANG TIM TRI ,  LAI TIN H ,  TRAN THUNGOC M

IPC: H04B3/14 ,  H04B3/06 ,  H04L25/03

CPC classification number: H04L25/03885

Abstract: PROBLEM TO BE SOLVED: To provide digital adaptation circuitry and method for programmable logic devices.
SOLUTION: This method provides for controlling equalization of an incoming data signal. The method includes detecting two successive differently valued bits in the data signal, determining whether transition in the incoming data signal between those bits occurs relatively late or relatively early, and increasing the equalization of the incoming data signal if it is relatively late.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为可编程逻辑器件提供数字适配电路和方法。 解决方案：该方法用于控制输入数据信号的均衡。 该方法包括检测数据信号中的两个连续的不同值的位，确定这些位之间的输入数据信号中的转换是否相对较晚或相对较早地发生，如果相对较晚，则增加输入数据信号的均衡。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007028614A

公开(公告)日：2007-02-01

申请号：JP2006190911

申请日：2006-07-11

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： TRAN THUNGOC ,  SHUMARAYEV SERGEY Y ,  HOANG TIM TRI ,  XUE NING ,  LEE CHONG ,  VENKATA RAMANAND

IPC: H03K19/173 ,  H04J99/00

CPC classification number: H03K19/17736 ,  H03K19/17744

Abstract: PROBLEM TO BE SOLVED: To reduce a downstream network load due to synchronization generated between the outputs of a four channel system, when four or more channels operate simultaneously. SOLUTION: The integrated circuit such as a programmable logic device (PLD) or the like includes multiple channels (30-0 to 30-3) of data communications circuitry. Circuitry is (54, 60) provided between these channels which are grouped in various sizes so as to selectively share signals. Thus, the device can appropriately support a communication protocol requesting various numbers of channels. The shared signals can include a clock signal, or an FIFO writing/reading permission signal. The circuit is preferably arranged in modules (that is, a certain channel and adjacent channels thereof, and/or a channel in a certain group and channels in neighboring groups thereof are equivalent or substantially equivalent) for facilitating the circuit design, circuit checking or the like. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：当四个或更多个信道同时工作时，由于四通道系统的输出之间产生的同步而减少下游网络负载。 解决方案：诸如可编程逻辑器件（PLD）等的集成电路包括数据通信电路的多个通道（30-0至30-3）。 在这些通道之间提供电路（54,60），其被分组成各种尺寸以便选择性地共享信号。 因此，设备可以适当地支持请求各种信道数量的通信协议。 共享信号可以包括时钟信号或FIFO写入/读取许可信号。 电路优选地布置在模块中（即，某个信道及其相邻信道，和/或某个组中的信道，并且相邻组中的信道相当于或基本相等），以便于电路设计，电路检查或 喜欢。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2011103678A

公开(公告)日：2011-05-26

申请号：JP2010291281

申请日：2010-12-27

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： WONG WILSON ,  CHAN DORIS PO CHING ,  SHUMARAYEV SERGEY ,  MAANGAT SIMARDEEP ,  HOANG TIM TRI ,  LAI TIN H ,  TRAN THUNGOC M

IPC: H04B3/04 ,  H04L25/03

CPC classification number: H04L25/03885

Abstract: PROBLEM TO BE SOLVED: To provide a digital adaptation circuitry and method for a programmable logic device. SOLUTION: A method of controlling equalization of an incoming data signal includes: detecting two continuous bits having different values in the data signal; determining whether transition in the incoming data signal between the two bits is relatively slow or relatively fast; and increasing the equalization of the incoming data signal when the transition is relatively slow. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：为可编程逻辑器件提供数字适配电路和方法。 控制输入​​数据信号的均衡的方法包括：检测数据信号中具有不同值的两个连续位; 确定两个位之间的输入数据信号中的转换是相对较慢还是相对较快; 并且当转换相对较慢时，增加输入数据信号的均衡。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2009153132A

公开(公告)日：2009-07-09

申请号：JP2008322994

申请日：2008-12-18

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： CARVALHO NEVILLE ,  DAVIDSON ALLAN THOMAS ,  TURUDIC ANDY ,  PEDERSEN BRUCE B ,  MENDEL DAVID W ,  KANKIPATI KALYAN ,  ZHENG MICHAEL MENGHUI ,  SHUMARAYEV SERGEY ,  PARK SEUNGMYON ,  HOANG TIM TRI ,  THARMALINGAM KUMARA

IPC: H04L7/033 ,  H03K19/173 ,  H03L7/08 ,  H04L13/08

CPC classification number: H04L25/14

Abstract: PROBLEM TO BE SOLVED: To provide a transceiver system having a reduced latency uncertainty. SOLUTION: The transceiver system has a word aligner with a latency uncertainty of zero. The system also has a bit slipper coupled with the word aligner. The bit slipper slips bits in such a manner that a total delay caused by word alignment of the word aligner and by a bit slip of the bit slipper is constant with respect to all phases of a recovery clock. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供具有减小的等待时间不确定性的收发机系统。

解决方案：收发器系统具有字符对准器，延迟不确定度为零。 该系统还具有与字对准器耦合的位拖鞋。 位拖动器以这样的方式滑动位，使得由字对准器的字对齐引起的总延迟和位拖动器的位滑动相对于恢复时钟的所有相位是恒定的。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：EP2332258A4

公开(公告)日：2014-02-26

申请号：EP09815015

申请日：2009-09-11

Applicant: ALTERA CORP

Inventor： HOANG TIM TRI ,  WONG WILSON ,  SHUMARAYEV SERGEY

IPC: H03L7/193 ,  H03L7/087

CPC classification number: H03L7/099 ,  H03L7/18

公开(公告)号：JP2014099925A

公开(公告)日：2014-05-29

申请号：JP2014030247

申请日：2014-02-20

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： HOANG TIM TRI ,  WONG WILSON ,  SHUMARAYEV SERGEY

IPC: H03L7/197 ,  H03L7/08 ,  H03L7/199

CPC classification number: H03L7/099 ,  H03L7/18

Abstract: PROBLEM TO BE SOLVED: To provide a technique for generating a fractional clock signal.SOLUTION: A circuit includes a phase detection circuit, a clock signal generation circuit, a first frequency divider and a second frequency divider. The phase detection circuit compares an input clock signal with a feedback signal to generate a control signal. The clock signal generation circuit generates a periodic output signal in response to the control signal. The first frequency divider divides a frequency of the periodic output signal by a first value to generate a first frequency-divided signal. The second frequency divider divides the frequency of the periodic output signal by a second value to generate a second frequency-divided signal. The first and second frequency-divided signals are routed to the phase detection circuit as the feedback signal during different time intervals.

Abstract translation: 要解决的问题：提供一种用于产生分数时钟信号的技术。解决方案：电路包括相位检测电路，时钟信号产生电路，第一分频器和第二分频器。 相位检测电路将输入时钟信号与反馈信号进行比较以产生控制信号。 时钟信号产生电路响应于控制信号产生周期性输出信号。 第一分频器将周期性输出信号的频率除以第一值以产生第一分频信号。 第二分频器将周期性输出信号的频率除以第二值，以产生第二分频信号。 在不同的时间间隔期间，第一和第二分频信号作为反馈信号被路由到相位检测电路。