公开(公告)号：WO2011133565A2

公开(公告)日：2011-10-27

申请号：PCT/US2011033071

申请日：2011-04-19

Applicant: ALTERA CORP ,  LI PENG ,  SHIMANOUCHI MASASHI ,  TRAN THUNGOC M ,  SHUMARAYEV SERGEY

Inventor： LI PENG ,  SHIMANOUCHI MASASHI ,  TRAN THUNGOC M ,  SHUMARAYEV SERGEY

IPC: G06F9/455 ,  G06F11/25 ,  G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5036 ,  G06F2217/10

Abstract: A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two- dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.

Abstract translation: 提供了一种用于模拟高速通信链路系统的链路仿真工具。 通信链路可以包括链路子系统，例如发射（TX）电路，接收（TX）电路，向TX和RX电路提供参考时钟信号的振荡器电路，以及链接TX和RX电路的信道。 链接仿真工具可以使用行为模型对每个子系统进行建模。 行为模型可以包括诸如传递函数，概率密度函数和眼睛特征的特征函数。 链接仿真工具可以具有能够执行二维（双变量）卷积运算并且对由行为模型提供的特征函数应用双域（频率 - 时间）变换以模拟性能的链路分析引擎 的链接系统。 链接仿真工具可以具有允许用户指定期望的链接参数的输入屏幕和显示模拟结果的数据显示屏幕。

公开(公告)号：WO2012030606A2

公开(公告)日：2012-03-08

申请号：PCT/US2011049068

申请日：2011-08-25

Applicant: ALTERA CORP ,  CHAN DORIS PO CHING ,  TRAN THUNGOC M

Inventor： CHAN DORIS PO CHING ,  TRAN THUNGOC M

IPC: H04L25/08 ,  H04L1/00 ,  H04L27/01

CPC classification number: H04L25/03057 ,  H04L25/03885 ,  H04L2025/0349 ,  H04L2025/03636

Abstract: Decision feedback equalizer ("DFE") circuitry bases determination of the coefficients that are used in its various taps on the algebraic sign of the current value of an error signal and prior serial data signal values output by the DFE circuitry. Use of such algebraic sign information (rather than full error signal values) greatly simplifies the circuitry needed to determine the tap coefficients. The DFE circuitry can be adaptive, i.e., such that it automatically adjusts the tap coefficients for changing serial data signal transmission conditions.

Abstract translation: 判决反馈均衡器（“DFE”）电路的基础是确定在其误差信号的当前值的代数符号上的各种抽头中使用的系数和由DFE电路输出的先前的串行数据信号值。 使用这种代数符号信息（而不是完整的误差信号值）极大地简化了确定抽头系数所需的电路。 DFE电路可以是自适应的，即，使得它自动调整用于改变串行数据信号传输条件的抽头系数。

公开(公告)号：WO2007019222A2

公开(公告)日：2007-02-15

申请号：PCT/US2006030248

申请日：2006-08-02

Applicant: ALTERA CORP ,  TRAN THUNGOC M ,  SHUMARAYEV SERGEY YURYEVICH ,  MAANGAT SIMARDEEP ,  WONG WILSON ,  PATEL RAKESH

Inventor： TRAN THUNGOC M ,  SHUMARAYEV SERGEY YURYEVICH ,  MAANGAT SIMARDEEP ,  WONG WILSON ,  PATEL RAKESH

IPC: H04L25/03

CPC classification number: H04L1/243 ,  H04L25/03878

Abstract: Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.

Abstract translation: 用于包含在PLD中的串行数据信号接收器电路包括串联连接并且可单独控制的多个均衡器电路，使得它们可以统一地补偿宽范围的可能的输入信号衰减特性。 其他电路特征可以相对于均衡器电路连接以给予接收机电路其他能力。 例如，这些其他特征可以包括各种类型的环回测试电路，可控终端电阻，可控共模电压以及用于检测输入信号的可控阈值。 接收器电路的控制的各个方面可以是可编程的。

公开(公告)号：JP2008072716A

公开(公告)日：2008-03-27

申请号：JP2007237202

申请日：2007-09-12

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： WONG WILSON ,  CHAN DORIS PO CHING ,  SHUMARAYEV SERGEY ,  MAANGAT SIMARDEEP ,  HOANG TIM TRI ,  LAI TIN H ,  TRAN THUNGOC M

IPC: H04B3/14 ,  H04B3/06 ,  H04L25/03

CPC classification number: H04L25/03885

Abstract: PROBLEM TO BE SOLVED: To provide digital adaptation circuitry and method for programmable logic devices.
SOLUTION: This method provides for controlling equalization of an incoming data signal. The method includes detecting two successive differently valued bits in the data signal, determining whether transition in the incoming data signal between those bits occurs relatively late or relatively early, and increasing the equalization of the incoming data signal if it is relatively late.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为可编程逻辑器件提供数字适配电路和方法。 解决方案：该方法用于控制输入数据信号的均衡。 该方法包括检测数据信号中的两个连续的不同值的位，确定这些位之间的输入数据信号中的转换是否相对较晚或相对较早地发生，如果相对较晚，则增加输入数据信号的均衡。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2011103678A

公开(公告)日：2011-05-26

申请号：JP2010291281

申请日：2010-12-27

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： WONG WILSON ,  CHAN DORIS PO CHING ,  SHUMARAYEV SERGEY ,  MAANGAT SIMARDEEP ,  HOANG TIM TRI ,  LAI TIN H ,  TRAN THUNGOC M

IPC: H04B3/04 ,  H04L25/03

CPC classification number: H04L25/03885

Abstract: PROBLEM TO BE SOLVED: To provide a digital adaptation circuitry and method for a programmable logic device. SOLUTION: A method of controlling equalization of an incoming data signal includes: detecting two continuous bits having different values in the data signal; determining whether transition in the incoming data signal between the two bits is relatively slow or relatively fast; and increasing the equalization of the incoming data signal when the transition is relatively slow. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：为可编程逻辑器件提供数字适配电路和方法。 控制输入​​数据信号的均衡的方法包括：检测数据信号中具有不同值的两个连续位; 确定两个位之间的输入数据信号中的转换是相对较慢还是相对较快; 并且当转换相对较慢时，增加输入数据信号的均衡。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：EP2561442A4

公开(公告)日：2016-10-19

申请号：EP11772564

申请日：2011-04-19

Applicant: ALTERA CORP

Inventor： LI PENG ,  SHIMANOUCHI MASASHI ,  TRAN THUNGOC M ,  SHUMARAYEV SERGEY

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5036 ,  G06F2217/10

Abstract: A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.

公开(公告)号：EP2612477A4

公开(公告)日：2015-03-11

申请号：EP11822374

申请日：2011-08-25

Applicant: ALTERA CORP

Inventor： CHAN DORIS PO CHING ,  TRAN THUNGOC M

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L25/03885 ,  H04L2025/0349 ,  H04L2025/03636

Abstract: Decision feedback equalizer (DFE) circuitry bases determination of the coefficients that are used in its various taps on the algebraic sign of the current value of an error signal and prior serial data signal values output by the DFE circuitry. Use of such algebraic sign information (rather than full error signal values) greatly simplifies the circuitry needed to determine the tap coefficients. The DFE circuitry can be adaptive, i.e., such that it automatically adjusts the tap coefficients for changing serial data signal transmission conditions.

公开(公告)号：JP2014064328A

公开(公告)日：2014-04-10

申请号：JP2013268773

申请日：2013-12-26

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： WONG WILSON ,  CHAN DORIS PO CHING ,  SHUMARAYEV SERGEY ,  MAANGAT SIMARDEEP ,  HOANG TIM TRI ,  LAI TIN H ,  TRAN THUNGOC M

IPC: H04L25/03 ,  H04B3/04

CPC classification number: H04L25/03885

Abstract: PROBLEM TO BE SOLVED: To provide a digital adaptive circuit network and a method for a programmable logic device.SOLUTION: A method controls equalization of an incoming data signal. The method comprises steps of: detecting bits having two consecutive different values out of the data signal; determining whether transition in the incoming data signal between the two bits is relatively low in speed or relatively high in speed; and increasing the equalization of the incoming data signal when the transition is relatively low in speed.

Abstract translation: 要解决的问题：提供数字自适应电路网络和可编程逻辑器件的方法。解决方案：一种控制输入数据信号的均衡的方法。 该方法包括以下步骤：从数据信号中检测具有两个连续不同值的位; 确定两个比特之间的输入数据信号中的转换是相对低的速度还是相对较高的速度; 并且当转换速度相对较低时，增加输入数据信号的均衡。

公开(公告)号：JP2011193505A

公开(公告)日：2011-09-29

申请号：JP2011100172

申请日：2011-04-27

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： WONG WILSON ,  CHAN DORIS PO CHING ,  SHUMARAYEV SERGEY ,  MAANGAT SIMARDEEP ,  HOANG TIM TRI ,  LAI TIN H ,  TRAN THUNGOC M

IPC: H04L25/03 ,  H04B3/06

CPC classification number: H04L25/03885

Abstract: PROBLEM TO BE SOLVED: To provide a digital adaptation circuit network and a method for a programmable logic device.
SOLUTION: The method controls the equalization of an incoming data signal. The method includes steps for: detecting bits having two consecutive different values out of the data signal; determining whether transition in the incoming data signal between the two bits is relatively low in speed or relatively high in speed; and increasing the equalization of the incoming data signal when the transition is relatively low in speed.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供数字适配电路网络和可编程逻辑器件的方法。

解决方案：该方法控制输入数据信号的均衡。 该方法包括以下步骤：从数据信号中检测具有两个连续不同值的位; 确定两个比特之间的输入数据信号中的转换是相对低的速度还是相对较高的速度; 并且当转换速度相对较低时，增加输入数据信号的均衡。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2007028619A

公开(公告)日：2007-02-01

申请号：JP2006192210

申请日：2006-07-12

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： ASADUZZAMAN KAZI ,  SHUMARAYEV SERGEY Y ,  TRAN THUNGOC M ,  WONG WILSON ,  PATEL RAKESH

IPC: H03K19/0175 ,  H03K5/12 ,  H03K17/687

CPC classification number: H03K17/164

Abstract: PROBLEM TO BE SOLVED: To variably control a slew rate in a transmitter to be used for data transfer employing variable slew rate or various transmission protocols.
SOLUTION: A transmitter driver circuit having a variable slew rate provided by the present invention comprises a pre-driver circuit for generating a driver input signal with a variable slew rate and a driver circuit for receiving a slew rate controlled signal from the pre-driver circuit. The pre-driver circuit comprises a plurality of pre-driver stages each selectively operable to drive a pre-driver output signal related to a signal received at an input and a control circuit which responds to at least one slew rate control signal, the control circuit operates to selectively enable the pre-driver stages and to change a pre-driver output signal slew rate, and the driver circuit generates a driver output signal with a slew rate related to a slew rate of the pre-driver output signal.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：可变地控制用于使用可变转换速率或各种传输协议的数据传输的发射机中的压摆率。 解决方案：由本发明提供的具有可变转换速率的发射器驱动电路包括用于产生具有可变转换速率的驱动器输入信号的预驱动器电路和用于从预先接收压摆率控制信号的驱动电路 驱动电路。 预驱动器电路包括多个预驱动器级，每个预驱动器级可选择性地操作以驱动与在输入处接收到的信号相关的预驱动器输出信号和响应于至少一个压摆率控制信号的控制电路，控制电路 操作以选择性地启用预驱动器级并改变预驱动器输出信号转换速率，并且驱动器电路产生具有与预驱动器输出信号的转换速率相关的转换速率的驱动器输出信号。 版权所有（C）2007，JPO＆INPIT