-
公开(公告)号:WO2022033793A1
公开(公告)日:2022-02-17
申请号:PCT/EP2021/069613
申请日:2021-07-14
Applicant: ASML NETHERLANDS B.V.
Inventor: COLLIGNON, Tijmen, Pieter , SMAL, Pavel , TABERY, Cyrus, Emil , DOS SANTOS GUZELLA, Thiago , BASTANI, Vahid
Abstract: Methods and associated apparatus for identifying contamination in a semiconductor fab are disclosed. The methods comprise determining contamination map data for a plurality of semiconductor wafers clamped to a wafer table after being processed in the semiconductor fab. Combined contamination map data is determined based, at least in part, on a combination of the contamination map data of the plurality of semiconductor wafers. The combined contamination map data is combined to reference data. The reference data comprises one or more values for the combined contamination map data that are indicative of contamination in one or more tools in the semiconductor fab.
-
公开(公告)号:WO2020108861A1
公开(公告)日:2020-06-04
申请号:PCT/EP2019/078529
申请日:2019-10-21
Applicant: ASML NETHERLANDS B.V.
Inventor: SMAL, Pavel , SOCHAL, Inez, Marlena , SARMA, Gautam
Abstract: A method for determining a layout of mark positions across a patterning device or substrate, the method comprising: a) obtaining (502) a model configured to model data associated with measurements performed on the patterning device or substrate at one or more mark positions; b) obtaining (504) an initial mark layout (506) comprising initial mark positions; c) reducing (508) the initial mark layout by removal of one or more mark positions to obtain a plurality of reduced mark layouts (510), each reduced mark layout obtained by removal of a different mark position from the initial mark layout; d) determining (512) a model uncertainty metric associated with usage of the model for each reduced mark layout out of said plurality of reduced mark layouts; and e) selecting (514) one or more reduced mark layouts (516) based on its associated model uncertainty metric.
-
公开(公告)号:EP3961303A1
公开(公告)日:2022-03-02
申请号:EP20193101.1
申请日:2020-08-27
Applicant: ASML Netherlands B.V.
Inventor: COLLIGNON, Tijmen Pieter , SMAL, Pavel , TABERY, Cyrus Emil
Abstract: Methods and associated apparatus for identifying contamination in a semiconductor fab are disclosed. The methods comprise determining contamination map data for a plurality of semiconductor wafers clamped to a wafer table after being processed in the semiconductor fab. Combined contamination map data is determined based, at least in part, on a combination of the contamination map data of the plurality of semiconductor wafers. The combined contamination map data is combined to reference data. The reference data comprises one or more values for the combined contamination map data that are indicative of contamination in one or more tools in the semiconductor fab.
-
公开(公告)号:EP4196851A1
公开(公告)日:2023-06-21
申请号:EP21740579.4
申请日:2021-07-14
Applicant: ASML Netherlands B.V.
-
公开(公告)号:EP4343472A1
公开(公告)日:2024-03-27
申请号:EP22196685.6
申请日:2022-09-20
Applicant: ASML Netherlands B.V.
Inventor: KOULIERAKIS, Eleftherios , GONZALEZ HUESCA, Juan Manuel , SMAL, Pavel , AARDEN, Frans, Bernard , RAVICHANDRAN, Arvind , DOU, Meng , HUBAUX, Arnaud , VAN HERTUM, Pieter
IPC: G05B19/418
Abstract: One embodiment relates to a method of classifying product units subject to a process performed by an apparatus, the method comprising: receiving KPI data, the KPI data associated with a plurality of components of the apparatus and comprising data associated with a plurality of KPIs; clustering the KPI data to identify a plurality of clusters; analyzing the plurality of clusters to identify a plurality of failure modes associated with the apparatus, for each identified failure mode assigning a threshold to each KPI associated with the failure mode; and for each of the plurality of product units: determining the likelihood of each of the plurality of failure modes based on KPI data of the product unit and the thresholds assigned to each KPI associated with one of the plurality of failure modes; and performing a classification based on the likelihoods of each of the plurality of failure modes.
-
公开(公告)号:EP3734363A1
公开(公告)日:2020-11-04
申请号:EP19171485.6
申请日:2019-04-29
Applicant: ASML Netherlands B.V.
Inventor: SMAL, Pavel , SOCHAL, Inez Marlena , SARMA, Gautam
Abstract: A method for determining a layout of mark positions across a patterning device or substrate, the method comprising: a) obtaining 502 a model configured to model data associated with measurements performed on the patterning device or substrate at one or more mark positions; b) obtaining 504 an initial mark layout 506 comprising initial mark positions; c) reducing 508 the initial mark layout by removal of one or more mark positions to obtain a plurality of reduced mark layouts 510, each reduced mark layout obtained by removal of a different mark position from the initial mark layout; d) determining 512 a model uncertainty metric associated with usage of the model for each reduced mark layout out of said plurality of reduced mark layouts; and e) selecting 514 one or more reduced mark layouts 516 based on its associated model uncertainty metric.
-
-
-
-
-