Abstract:
PURPOSE: An apparatus and a method for providing resist aligning marks in a dual patterning lithography process are provided to reinforce the symmetric property of the aligning marks by regulating the thickness of resist layers. CONSTITUTION: A substrate is coated with a first resist layer(1010). A first resist layer is developed to form a first lithography pattern with a first aligning mark(1020). A first lithography pattern is frozen(1030). The frozen first lithography pattern is coated with a second resist layer(1040). The second resist layer is hardened to form a second aligning mark(1050). The second aligning mark is used for perform a successive lithography process(1060).
Abstract:
PROBLEM TO BE SOLVED: To improve the contrast of an alignment mark, in such a lithography patterning method as a double patterning method for improving the resolution of an optical lithography. SOLUTION: A system, method, and product for manufacturing a semiconductor device by a lithography which are accompanied by a lithography double patterning process for adding a coloring matter to a first or second lithography pattern are provided. A position of the first lithography pattern is detected, and for aligning the second lithography pattern with the position directly, the coloring matter is used. The contrast of the alignment mark is the property of a fluorescence, light emission, light absorption, or light reflection in a specific or predetermined wavelength region. The used wavelength may coincide with the wavelength of the alignment beam. The coloring matter is detected even when the coloring matter is finished by a radiation sensing layer (for example, a resist). COPYRIGHT: (C)2011,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide a method for positioning a substrate during a double patterning lithography process. SOLUTION: A first resist layer including at least one alignment mark is formed on a substrate. After the first resist layer is developed, a second resist layer is deposited on the first resist layer, and thereby a flat upper surface is left (namely, there is no topography). The second resist layer is suitably baked to form a symmetrical alignment mark in the second resist layer without or substantially without an offset error from the alignment mark in the first resist layer. Symmetry of the alignment mark formed in the second resist layer is improved by suitably adjusting thicknesses, coating process parameters, and baking process parameters of the first and the second resist layers. COPYRIGHT: (C)2011,JPO&INPIT