公开(公告)号：US20150115469A1

公开(公告)日：2015-04-30

申请号：US14523733

申请日：2014-10-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chun-Che LEE ,  Ming-Chiang LEE

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2224/16225 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/007 ,  H05K3/4682 ,  H05K2201/09227 ,  H05K2201/09563 ,  H05K2201/09772 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.

Abstract translation: 提供半导体基板及其制造方法。 半导体衬底包括电介质层，电路层，第一保护层和多个导电柱。 电介质层具有彼此相对的第一表面和第二表面。 电路层嵌入电介质层并从第一表面露出。 第一保护层覆盖第一电路层的一部分并且限定暴露第一电路层的剩余部分的多个孔。 导电柱形成在孔中。

公开(公告)号：US20160225708A1

公开(公告)日：2016-08-04

申请号：US15006306

申请日：2016-01-26

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Chun-Che LEE ,  Sheng-Ming WANG ,  Kuang-Hsiung CHEN ,  Yu-Ying LEE

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/288 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor substrate includes an insulating layer and a conductive circuit layer embedded at a surface of the insulating layer. The conductive circuit layer includes a first portion and a second portion. The first portion includes a bonding pad and one portion of a conductive trace, and the second portion includes another portion of the conductive trace. An upper surface of the first portion is not coplanar with an upper surface of the second portion. A semiconductor packaging structure includes the semiconductor substrate.

Abstract translation: 半导体衬底包括绝缘层和埋在绝缘层的表面上的导电电路层。 导电电路层包括第一部分和第二部分。 第一部分包括接合焊盘和导电迹线的一部分，并且第二部分包括导电迹线的另一部分。 第一部分的上表面不与第二部分的上表面共面。 半导体封装结构包括半导体衬底。

公开(公告)号：US20220359361A1

公开(公告)日：2022-11-10

申请号：US17873085

申请日：2022-07-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chun-Che LEE ,  Ming-Chiang LEE ,  Yuan-Chang SU ,  Tien-Szu CHEN ,  Chih-Cheng LEE ,  You-Lung YEN

IPC: H01L23/498 ,  H05K1/11 ,  H05K3/00 ,  H01L21/48

Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.

公开(公告)号：US20140367837A1

公开(公告)日：2014-12-18

申请号：US14303371

申请日：2014-06-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chun-Che LEE ,  Yuan-Chang SU ,  Wen-Chi CHENG ,  Guo-Cheng LIAO ,  Yi-Chuan DING

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L23/13 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/11019 ,  H01L2224/11622 ,  H01L2224/1163 ,  H01L2224/13147 ,  H01L2224/14104 ,  H01L2224/16225 ,  H01L2924/12042 ,  H05K3/108 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/09045 ,  H05K2201/10674 ,  H05K2203/0723 ,  H05K2203/1461 ,  H01L2924/00

Abstract: The present disclosure relates to a semiconductor substrate and a method for making the same. The semiconductor substrate includes an insulation layer, a first circuit layer, a second circuit layer, a plurality of conductive vias and a plurality of bumps. The first circuit layer is embedded in a first surface of the insulation layer, and exposed from the first surface of the insulation layer. The second circuit layer is located on a second surface of the insulation layer and electrically connected to the first circuit layer through the conductive vias. The bumps are directly located on part of the first circuit layer, where the lattice of the bumps is the same as that of the first circuit layer.

Abstract translation: 本公开涉及一种半导体衬底及其制造方法。 半导体衬底包括绝缘层，第一电路层，第二电路层，多个导电通孔和多个凸块。 第一电路层嵌入绝缘层的第一表面，并从绝缘层的第一表面露出。 第二电路层位于绝缘层的第二表面上，并通过导电通孔与第一电路层电连接。 凸块直接位于第一电路层的一部分上，其中凸块的晶格与第一电路层的晶格相同。