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    초음파 트랜스듀서 디바이스들 및 초음파 트랜스듀서 디바이스들을 제조하기 위한 방법들
    1.
    发明公开
    초음파 트랜스듀서 디바이스들 및 초음파 트랜스듀서 디바이스들을 제조하기 위한 방법들 审中-公开

    公开(公告)号：KR20200130375A

    公开(公告)日：2020-11-18

    申请号：KR20207028604

    申请日：2019-03-08

    Applicant: BUTTERFLY NETWORK INC

    Inventor： FIFE KEITH G ,  LIU JIANWEI

    IPC: B06B1/02 ,  H05K1/11 ,  H05K3/46

    Abstract: 본명세서에설명된기술의양태들은 CMUT(capacitive micromachined ultrasonic transducer)들을포함하는초음파트랜스듀서디바이스들및 초음파트랜스듀서디바이스들에서 CMUT들을형성하기위한방법들에관한것이다. 일부실시예들은제1 기판상에절연재료의제1 층을형성하고, 절연재료의제1 층상에절연재료의제2 층을형성하고, 그후 제2 절연재료에캐비티를에칭함으로써, CMUT의캐비티를형성하는것을포함한다. 캐비티를밀봉하기위해제2 기판이제1 기판에본딩될수 있다. 절연재료의제1 층은, 예를들어, 알루미늄산화물을포함할수 있다. 제1 기판은집적회로를포함할수 있다. 일부실시예들은제1 및제2 절연층들을형성하기전에(TSV-중간프로세스) 또는제1 및제2 기판들을본딩하는것에후속하여(TSV-최종프로세스) 관통실리콘비아(TSV)들을제1 기판에형성하는것을포함한다.

    Ultrasound transducer devices and methods for fabricating ultrasound transducer devices
    5.
    发明专利
    Ultrasound transducer devices and methods for fabricating ultrasound transducer devices 未知

    公开(公告)号：AU2019231793A1

    公开(公告)日：2020-09-24

    申请号：AU2019231793

    申请日：2019-03-08

    Applicant: BUTTERFLY NETWORK INC

    Inventor： FIFE KEITH G ,  LIU JIANWEI

    IPC: B06B1/00 ,  B81B3/00 ,  B81C1/00 ,  G10K9/12 ,  G10K11/18

    Abstract: Aspects of the technology described herein relate to ultrasound transducer devices including capacitive micromachined ultrasonic transducers (CMUTs) and methods for forming CMUTs in ultrasound transducer devices. Some embodiments include forming a cavity of a CMUT by forming a first layer of insulating material on a first substrate, forming a second layer of insulating material on the first layer of insulating material, and then etching a cavity in the second insulating material. A second substrate may be bonded to the first substrate to seal the cavity. The first layer of insulating material may include, for example, aluminum oxide. The first substrate may include integrated circuitry. Some embodiments include forming through- silicon vias (TSVs) in the first substrate prior to forming the first and second insulating layers (TSV-Middle process) or subsequent to bonding the first and second substrates (TSV-Last process).

    METHODS AND APPARATUSES FOR PACKAGING AN ULTRASOUND-ON-A-CHIP
    7.
    发明专利
    METHODS AND APPARATUSES FOR PACKAGING AN ULTRASOUND-ON-A-CHIP 未知

    公开(公告)号：CA3105492A1

    公开(公告)日：2020-01-09

    申请号：CA3105492

    申请日：2019-07-03

    Applicant: BUTTERFLY NETWORK INC

    Inventor： LIU JIANWEI ,  FIFE KEITH G

    IPC: G01N29/22 ,  A61B8/00

    Abstract: Described herein are methods and apparatuses for packaging an ultrasound-on-a-chip. An ultrasound-on-a-chip may be coupled to a redistribution layer and to an interposer layer. Encapsulation may encapsulate the ultrasound-on-a-chip device and first metal pillars may extend through the encapsulation and electrically couple to the redistribution layer. Second metal pillars may extend through the interposer layer. The interposer layer may include aluminum nitride. The first metal pillars may be electrically coupled to the second metal pillars. A printed circuit board may be coupled to the interposer layer.

    ULTRASOUND TRANSDUCER DEVICES AND METHODS FOR FABRICATING ULTRASOUND TRANSDUCER DEVICES
    9.
    发明专利
    ULTRASOUND TRANSDUCER DEVICES AND METHODS FOR FABRICATING ULTRASOUND TRANSDUCER DEVICES 未知

    公开(公告)号：CA3092139A1

    公开(公告)日：2019-09-12

    申请号：CA3092139

    申请日：2019-03-08

    Applicant: BUTTERFLY NETWORK INC

    Inventor： FIFE KEITH G ,  LIU JIANWEI

    IPC: B06B1/00 ,  B81B3/00 ,  B81C1/00 ,  G10K9/12 ,  G10K11/18

    Abstract: Aspects of the technology described herein relate to ultrasound transducer devices including capacitive micromachined ultrasonic transducers (CMUTs) and methods for forming CMUTs in ultrasound transducer devices. Some embodiments include forming a cavity of a CMUT by forming a first layer of insulating material on a first substrate, forming a second layer of insulating material on the first layer of insulating material, and then etching a cavity in the second insulating material. A second substrate may be bonded to the first substrate to seal the cavity. The first layer of insulating material may include, for example, aluminum oxide. The first substrate may include integrated circuitry. Some embodiments include forming through- silicon vias (TSVs) in the first substrate prior to forming the first and second insulating layers (TSV-Middle process) or subsequent to bonding the first and second substrates (TSV-Last process).

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