公开(公告)号：WO1994008293A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009431

申请日：1993-09-30

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  LANDRY, John, A. ,  WOLFORD, Jeff, W. ,  FRY, Walter, G. ,  TIPLEY, Roger, E.

IPC: G06F11/20

CPC classification number: G06F11/1637 ,  G06F11/1679

Abstract: A method and apparatus for operating tightly coupled mirrored processors in a computer system. A plurality of CPU boards are coupled to a processor/memory bus, commonly called a host bus. Each CPU board includes a processor as well as various ports, timers, and interrupt controller logic local to the respective processor. The processors on one or more CPU boards are designated as master processors, with the processors on the remaining CPU boards being designated as mirroring or slave processors. A master processor has full access to the host bus and a second, multiplexed bus for read and write cycles, whereas the slave processors are prevented from writing to any bus. The slave processors compare write data and various control signals with that generated by its respective master processor for disparities. The system includes interrupt controller synchronization logic to synchronize interrupt requests as well as timer synchronization logic to synchronize the timers in each of the master and slave CPUs to guarantee that the master and slave CPUs operate in lockstep.

Abstract translation: 一种用于在计算机系统中操作紧耦合的镜像处理器的方法和装置。 多个CPU板耦合到通常称为主机总线的处理器/存储器总线。 每个CPU板包括一个处理器以及各个处理器本地的各种端口，定时器和中断控制器逻辑。 一个或多个CPU板上的处理器被指定为主处理器，其余CPU板上的处理器被指定为镜像或从属处理器。 主处理器具有对主机总线的完全访问和用于读和写周期的第二复用总线，而从处理器被阻止写入任何总线。 从处理器将写入数据和各种控制信号与其相应的主处理器产生的差异进行比较。 该系统包括中断控制器同步逻辑，以同步中断请求以及定时器同步逻辑，以同步每个主CPU和从CPU的定时器，以保证主CPU和从CPU处于锁定状态。

公开(公告)号：WO1994008301A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009186

申请日：1993-09-24

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  TIPLEY, Roger, E. ,  MORIARTY, Michael ,  TAYLOR, Mark

IPC: G06F13/36

CPC classification number: G06F13/36 ,  G06F13/364

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allow a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

Abstract translation: 用于确定多个CPU中的哪一个接收优先权以成为多处理器系统中的主机总线的总线的三个优先级方案，以及用于将控制从一个总线主机传送到另一个总线主机的仲裁方案。 每个优先排序方案优先考虑n个元素，其中总共（n / 2）x（n-1）个优先级位监视每对元素之间的相对优先级。 当与该元素相关联的n-1个优先级位中的每一个指向它时，元素接收最高优先级。 在仲裁方案中，主机总线的当前总线主机确定主机总线的控制何时发生，由优先级排列方案之一决定。 仲裁方案给予EISA总线主机，RAM刷新和DMA优先于作为总线主机的CPU，并允许临时总线主机中断当前总线主机以执行回写高速缓存干预周期。 仲裁方案还支持在尝试锁定循环时中止CPU的地址流水线，突发，拆分事务和预留。 地址流水线允许下一个总线主机在下一个总线主机的数据传输阶段开始之前断言其地址和状态信号。 拆分事务允许CPU向EISA总线发布读取，以将主机总线仲裁到另一个设备，而不需要重新仲裁主机总线来检索数据。 即使主机总线被其他设备控制，数据在空闲时也在主机总线上被断言。

公开(公告)号：WO1994008304A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009369

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  TAYLOR, Mark ,  CULLEY, Paul, R. ,  MELO, Maria, L. ,  TIPLEY, Roger, E.

IPC: G06F13/364

CPC classification number: G06F13/364

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allow a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

Abstract translation: 用于确定多个CPU中的哪一个接收优先权以成为多处理器系统中的主机总线的总线的三个优先级方案，以及用于将控制从一个总线主机传送到另一个总线主机的仲裁方案。 每个优先排序方案优先考虑n个元素，其中总共（n / 2）x（n-1）个优先级位监视每对元素之间的相对优先级。 当与该元素相关联的n-1个优先级位中的每一个指向它时，元素接收最高优先级。 在仲裁方案中，主机总线的当前总线主机确定主机总线的控制何时发生，由优先级排列方案之一决定。 仲裁方案给予EISA总线主机，RAM刷新和DMA优先于作为总线主机的CPU，并允许临时总线主机中断当前总线主机以执行回写高速缓存干预周期。 仲裁方案还支持在尝试锁定循环时中止CPU的地址流水线，突发，拆分事务和预留。 地址流水线允许下一个总线主机在下一个总线主机的数据传输阶段开始之前断言其地址和状态信号。 拆分事务允许CPU向EISA总线发布读取，以将主机总线仲裁到另一个设备，而不需要重新仲裁主机总线来检索数据。 即使主机总线被其他设备控制，数据在空闲时也在主机总线上被断言。

公开(公告)号：EP0664032A1

公开(公告)日：1995-07-26

申请号：EP93924909.0

申请日：1993-09-29

Applicant: Compaq Computer Corporation

Inventor： TAYLOR, Mark ,  CULLEY, Paul, R. ,  MELO, Maria, L. ,  TIPLEY, Roger, E.

IPC: G06F13

CPC classification number: G06F13/364

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allow a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

公开(公告)号：EP0664031B1

公开(公告)日：1997-01-22

申请号：EP93924899.3

申请日：1993-09-24

Applicant: Compaq Computer Corporation

Inventor： TIPLEY, Roger, E. ,  MORIARTY, Michael ,  TAYLOR, Mark

IPC: G06F13/36 ,  G06F13/364

CPC classification number: G06F13/36 ,  G06F13/364

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allow a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

公开(公告)号：EP0664031A1

公开(公告)日：1995-07-26

申请号：EP93924899.0

申请日：1993-09-24

Applicant: Compaq Computer Corporation

Inventor： TIPLEY, Roger, E. ,  MORIARTY, Michael ,  TAYLOR, Mark

IPC: G06F13

CPC classification number: G06F13/36 ,  G06F13/364

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allow a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.