公开(公告)号：JPH08272885A

公开(公告)日：1996-10-18

申请号：JP28281995

申请日：1995-10-31

Applicant: CONS RIC MICROELETTRONICA

Inventor： DARIO BURUUNO ,  BIAJIYO JIYAKAROONE ,  NIKORO MANAREESHI

IPC: G06G7/12 ,  G05F3/24 ,  G06N7/04

Abstract: PROBLEM TO BE SOLVED: To obtain an analog device for antecedent count of a fuzzy reference rule by providing an output which acquire an entire truth degree that is related to a fuzzy rule antecedent part to be processed to an one-way element. SOLUTION: A processor 2 contains plural membership function FA analog generators 3. These generators 3 are acquired by a Sasaki generator. Each generator 3 presents an output terminal 4 which is connected to a common circuit node 7. The node 7 is connected to a current generator 9 which sequentially sends out current Imax , a voltage controller 5, a voltage pull-up device 6 and also an one-way element 8. The element 8 constitutes an output 10 of the processor 2.

公开(公告)号：JPH07271593A

公开(公告)日：1995-10-20

申请号：JP5921395

申请日：1995-03-17

Applicant: CONS RIC MICROELETTRONICA

Inventor： MATSUSHIMO ABURUZETSUSE ,  BIAJIYO JIYAKAROONE

IPC: G06F9/44 ,  G06N7/02 ,  G06N7/04

Abstract: PURPOSE: To eliminate the disadvantage of the conventional technique while the high calculating speed of membership functions and the optimization of storage are maintained. CONSTITUTION: In a method for storing the membership function (FA) of a logical variable defined in a discussed region (U) distinguished with a finite number of points (m), the apex of each membership function is stored in the first part of the corresponding stored word and the inclination on each side of the apex is stored in the second and third parts.

公开(公告)号：JPH07271592A

公开(公告)日：1995-10-20

申请号：JP5921495

申请日：1995-03-17

Applicant: CONS RIC MICROELETTRONICA

Inventor： MATSUSHIMO ABURUZETSUSE ,  BIAJIYO JIYAKAROONE

IPC: G06F9/44 ,  G05B13/02 ,  G06N7/02 ,  G06N7/04

Abstract: PURPOSE: To reconstitute the expectation value α a membership function (FA) stored as a significant value at each point in a discussed region (U). CONSTITUTION: A calculation circuit 8 is provided with a microprocessor 9, a storing section 5, an interface 13, and a calculator 11. The storing section 5 stores FAs from the microprocessor 9 and the calculator 11 is connected to the storing section 5, microprocessor 9, and interface 13 and decides the value of each FA at each point in the U by using the stored apexes and inclinations of the FA.

公开(公告)号：JPH07319704A

公开(公告)日：1995-12-08

申请号：JP11600195

申请日：1995-05-15

Applicant: CONS RIC MICROELETTRONICA

Inventor： BIAJIYO JIYAKAROONE ,  BUINCHIENTSUO KATANIA ,  KURAUDEIO RUTSUTSUI ,  BUINCHIENTSUO MATORANGA

IPC: G06F9/44 ,  G06N7/02 ,  G06N7/04 ,  H03K19/20

Abstract: PURPOSE: To provide a parallel processing method and the circuit constitution for many fuzzy rules independent of the premise part of a rule or the number of terms constituting a logical operator connecting the rules. CONSTITUTION: An inference unit 1 includes plural same inference processing lines 2 having a module structure which are connected in parallel between a data bus and a connecting block 19, and each includes an evaluation block 3, calculation block 4, and consequent part processing block 5 in a belonging relation, and those blocks 3, 4, and 5 are serially connected.

公开(公告)号：JPH07319703A

公开(公告)日：1995-12-08

申请号：JP11600095

申请日：1995-05-15

Applicant: CONS RIC MICROELETTRONICA

Inventor： BUINCHIENTSUO MATORANGA ,  BIAJIYO JIYAKAROONE ,  MATSUSHIMO ABURUZETSUSE

IPC: G06F9/44 ,  G06N7/02 ,  G06N7/04 ,  H03K19/20

Abstract: PURPOSE: To operate the simultaneous processing of several rules for designing a fuzzy logic by relating a logical operator with the maximum and minimum operation, and completely calculating the full levels of the truth of a rule as the maximum value or the minimum value of N pieces of partial true levels. CONSTITUTION: Four same circuits 2 are provided inside an inference unit 1, and each circuit 2 is provided with two input terminals 11 and 12 and an output terminal O. The input terminal 11 receives one set of data ALFA, each ALFA are encoded by 16 bits, and the data has the value of weight to be processed. The input terminal 12 receives one set of logical operators OPC, and those OPC are encoded by 3 bits for a logical operation to be executed. This logical operator OPC is made correspond to the maximum and minimum fuzzy logical operation, and an inference rule value OMEGA is supplied to the output terminal O. Then, the full levels of the truth of a rule is calculated based on a partial true model from the value OMEGA, and a parallel processing is operated.