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1.
公开(公告)号:JPH07319704A
公开(公告)日:1995-12-08
申请号:JP11600195
申请日:1995-05-15
Applicant: CONS RIC MICROELETTRONICA
Inventor: BIAJIYO JIYAKAROONE , BUINCHIENTSUO KATANIA , KURAUDEIO RUTSUTSUI , BUINCHIENTSUO MATORANGA
Abstract: PURPOSE: To provide a parallel processing method and the circuit constitution for many fuzzy rules independent of the premise part of a rule or the number of terms constituting a logical operator connecting the rules. CONSTITUTION: An inference unit 1 includes plural same inference processing lines 2 having a module structure which are connected in parallel between a data bus and a connecting block 19, and each includes an evaluation block 3, calculation block 4, and consequent part processing block 5 in a belonging relation, and those blocks 3, 4, and 5 are serially connected.
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2.
公开(公告)号:JPH07319703A
公开(公告)日:1995-12-08
申请号:JP11600095
申请日:1995-05-15
Applicant: CONS RIC MICROELETTRONICA
Abstract: PURPOSE: To operate the simultaneous processing of several rules for designing a fuzzy logic by relating a logical operator with the maximum and minimum operation, and completely calculating the full levels of the truth of a rule as the maximum value or the minimum value of N pieces of partial true levels. CONSTITUTION: Four same circuits 2 are provided inside an inference unit 1, and each circuit 2 is provided with two input terminals 11 and 12 and an output terminal O. The input terminal 11 receives one set of data ALFA, each ALFA are encoded by 16 bits, and the data has the value of weight to be processed. The input terminal 12 receives one set of logical operators OPC, and those OPC are encoded by 3 bits for a logical operation to be executed. This logical operator OPC is made correspond to the maximum and minimum fuzzy logical operation, and an inference rule value OMEGA is supplied to the output terminal O. Then, the full levels of the truth of a rule is calculated based on a partial true model from the value OMEGA, and a parallel processing is operated.
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