公开(公告)号：JPH08279737A

公开(公告)日：1996-10-22

申请号：JP29860695

申请日：1995-11-16

Applicant: CONS RIC MICROELETTRONICA ,  SGS THOMSON MICROELECTRONICS

Inventor： PAORO KORETSUTEI ,  GUREGORIO BONTENPO ,  FURANCHIESUKO PURUBUIRENTEI ,  ROBERUTO GARIBORUDEI

IPC: H01L27/04 ,  G05F1/573 ,  H01L21/822 ,  H01L29/78 ,  H02H7/00 ,  H03K17/08

Abstract: PROBLEM TO BE SOLVED: To provide a simple and correct method for protecting a power transistor(TR). SOLUTION: The method is provided with a process where a 1st electric signal S1 proportional substantially to a current flowing to a path D-S is generated, a process where a 2nd electric signal S2 proportional substantially to a voltage across the path D-S is generated, a process where the 1st signal S1 and the 2nd signal S2 are multiplied to generate an electric generating signal PS, a process where the electric generating signal PS is compared with an electric reference signal RS to generate an electric difference signal DS, and a process where the electric difference signal DS is used to drive a control terminal G so that the electric generating signal PS is smaller than the reference signal RS.

公开(公告)号：JPH08107629A

公开(公告)日：1996-04-23

申请号：JP14207495

申请日：1995-06-08

Applicant: CONS RIC MICROELETTRONICA

Inventor： GUREGORIO BONTENPO ,  FURANCHIESUKO PURUBUIRENTEI ,  PAORO KORETSUTEI ,  ROBERUTO GARIBORUDEI

IPC: H02H3/08 ,  H03K17/082 ,  H03K17/284

Abstract: PURPOSE: To independently control on-times and off-times of multiplex independent channels by a method, wherein a generating circuit which generates on times and off-times of integrated switches is connected between the input terminal of a 1st logic gate and the output of an output device. CONSTITUTION: A comparator 5, a logic gate PL1, a driver 6, a DMOS transistor Tr7 and an output terminal S1 are connected in series with the input part 2 of an overload protective device 13. The drain D1 of the transistor Tr7 is inputted to an operational amplifier 9, whose output 03 is fed back to the driver 6. A circuit A which generates on-times and off-times of integrated switches is provided between the output 04 of the amplifier 9 and the logic gate PL1. In the circuit A, the output of a capacitor C1 and a free-running type oscillator 14 is inputted to a logic gate PL2 and the on-times and off-times of respective channels are set by a storage block 16 and a counter block 15. The set on-times and off-times are inputted to the logic gate PL1. With this constitution, an interval between the on-times and off-times can be set for every channel.