SLEWING SPEED CONTROL IN POWER STAGE AND OPTIMIZATION OF POWER CONSUMPTION AND DEVICE

    公开(公告)号:JPH07326953A

    公开(公告)日:1995-12-12

    申请号:JP15230995

    申请日:1995-05-25

    Abstract: PURPOSE: To optimize power consumption and switching delay by changing the operational condition of an output power transistor(TR) and attaining current absorption in accordance with a current level transmitted by a driving operational amplifier. CONSTITUTION: The driving operational amplifier 15 constituted of a differential input stage consisting of current mirrors 1 to 3 constituting a final stage, a differential TR pair N1 , N2 and a current oscillator IP. The single ends of these mirrors 1 to 3 are directly connected to the gate of the output power TR PW and the current absorption of output currents having the same level on the differential input stage is reduced in accordance with a mirror ratio. An output current from the amplifier is modulated by circuit arrangement consisting of TRs M1 , M2 , P1 to P4 , and an auxiliary current oscillator I while relating to the operation state of the circuit and the TR pair M1 , M2 is cross- coupled with the TR pair N1 , N2 . Thus a current necessary for the charging and discharging the gate node of the TR PW1 is transmitted from the operational amplifier.

    EQUIPMENT AND METHOD FOR OVERLOAD PROTECTION TO PROTECT INTEGRATED CIRCUIT FROM ELECTRIC CURRENT OVERLOAD

    公开(公告)号:JPH08107629A

    公开(公告)日:1996-04-23

    申请号:JP14207495

    申请日:1995-06-08

    Abstract: PURPOSE: To independently control on-times and off-times of multiplex independent channels by a method, wherein a generating circuit which generates on times and off-times of integrated switches is connected between the input terminal of a 1st logic gate and the output of an output device. CONSTITUTION: A comparator 5, a logic gate PL1, a driver 6, a DMOS transistor Tr7 and an output terminal S1 are connected in series with the input part 2 of an overload protective device 13. The drain D1 of the transistor Tr7 is inputted to an operational amplifier 9, whose output 03 is fed back to the driver 6. A circuit A which generates on-times and off-times of integrated switches is provided between the output 04 of the amplifier 9 and the logic gate PL1. In the circuit A, the output of a capacitor C1 and a free-running type oscillator 14 is inputted to a logic gate PL2 and the on-times and off-times of respective channels are set by a storage block 16 and a counter block 15. The set on-times and off-times are inputted to the logic gate PL1. With this constitution, an interval between the on-times and off-times can be set for every channel.

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