公开(公告)号：EP0811928A3

公开(公告)日：1999-02-10

申请号：EP97303793.0

申请日：1997-06-04

Applicant: Compaq Computer Corporation

Inventor： Goodrum, Alan L. ,  Ramsey, Jens K. ,  Culley, Paul R. ,  Miller, Joseph P.

IPC: G06F13/40

CPC classification number: G06F13/405

Abstract: Data is transmitted between a first device and a second device connected by the communications channel in a computer system. The first device generates a first clock and the second device generates a second clock. The first clock is provided to the second device and the second clock is provided to the first device. Data received by the first device over the communications channel from the second device is synchronized to the first clock. The receiving logic in the first device includes a first-in-first-out buffer. The received data is stored in a first-in-first-out buffer until the data is synchronized to the first clock. The first and second clocks have the same frequency.

公开(公告)号：EP0811928A2

公开(公告)日：1997-12-10

申请号：EP97303793.0

申请日：1997-06-04

Applicant: Compaq Computer Corporation

Inventor： Goodrum, Alan L. ,  Ramsey, Jens K. ,  Culley, Paul R. ,  Miller, Joseph P.

IPC: G06F13/40

CPC classification number: G06F13/405

Abstract: Data is transmitted between a first device and a second device connected by the communications channel in a computer system. The first device generates a first clock and the second device generates a second clock. The first clock is provided to the second device and the second clock is provided to the first device. Data received by the first device over the communications channel from the second device is synchronized to the first clock. The receiving logic in the first device includes a first-in-first-out buffer. The received data is stored in a first-in-first-out buffer until the data is synchronized to the first clock. The first and second clocks have the same frequency.

Abstract translation: 在计算机系统中，通过通信信道连接的第一设备和第二设备之间传送数据。 第一设备产生第一时钟，第二设备产生第二时钟。 第一时钟被提供给第二设备，并且第二时钟提供给第一设备。 由第一设备通过通信信道从第二设备接收的数据被同步到第一时钟。 第一设备中的接收逻辑包括先进先出缓冲器。 接收的数据被存储在先进先出缓冲器中，直到数据与第一时钟同步。 第一和第二时钟具有相同的频率。

公开(公告)号：EP0811924A2

公开(公告)日：1997-12-10

申请号：EP97303799.7

申请日：1997-06-04

Applicant: Compaq Computer Corporation

Inventor： Ramsey, Jens K. ,  Goodrum, Alan L. ,  Culley, Paul R.

IPC: G06F13/364

CPC classification number: G06F13/364

Abstract: Access to a bus in a computer system having a CPU and bus devices capable of running cycles on a bus is controlled by an arbiter. The arbiter grants access to the bus according to an arbitration scheme that depends on whether a request for the bus is pending from the CPU, in which a first arbitration scheme arbitrates between the bus devices, and wherein a second arbitration scheme arbitrates between the CPU and at least one other bus device if the CPU request is present.

Abstract translation: 具有能够在总线上运行周期的CPU和总线设备的计算机系统中的总线的访问由仲裁器控制。 仲裁器根据仲裁方案授权对总线的访问，该仲裁方案取决于来自CPU的总线请求是否等待，其中第一仲裁方案在总线设备之间进行仲裁，并且其中第二仲裁方案在CPU和 如果存在CPU请求，则至少另外一个总线设备。

公开(公告)号：EP0707256A3

公开(公告)日：1996-08-07

申请号：EP95307348.3

申请日：1995-10-13

Applicant: Compaq Computer Corporation

Inventor： Ramsey, Jens K. ,  Tubbs, Michael E. ,  Stevens, Jeffrey C. ,  Stancil, Charles J.

IPC: G06F1/32 ,  G06F12/08

CPC classification number: G06F1/3215 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3268 ,  G06F1/3275 ,  G06F9/30083 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0833 ,  G06F2212/1028 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/154

Abstract: A circuit is described for placing an external or L2 cache memory into low power mode in response to certain special cycles executed by a microprocessor. In particular, the special cycles may be the stop grant acknowledge special cycle and the halt special cycle. The microprocessor executes the stop grant acknowledge special cycle in response to a request by the computer system to slow down its clock. This request is asserted by the computer system if the system has been idle for a predetermined period of time. The halt special cycle is generated by the microprocessor when a HALT instruction is executed. The stop grant acknowledge and halt special cycles place the microprocessor into a low power state. Since the microprocessor is in low power mode, the L2 cache memory is also placed into low power mode for further power conservation. The L2 cache memory is implemented either with synchronous or asynchronous static random access memories (SRAMs). To place a synchronous SRAM into low power mode, its address strobe input is asserted while its chip select input is deasserted. For an asynchronous SRAM, deasserting its chip select input causes the SRAM to transition into low power mode.

公开(公告)号：EP0707256A2

公开(公告)日：1996-04-17

申请号：EP95307348.3

申请日：1995-10-13

Applicant: Compaq Computer Corporation

Inventor： Ramsey, Jens K. ,  Tubbs, Michael E. ,  Stevens, Jeffrey C. ,  Stancil, Charles J.

IPC: G06F1/32 ,  G06F12/08

CPC classification number: G06F1/3215 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3268 ,  G06F1/3275 ,  G06F9/30083 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0833 ,  G06F2212/1028 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/154

Abstract: A circuit is described for placing an external or L2 cache memory into low power mode in response to certain special cycles executed by a microprocessor. In particular, the special cycles may be the stop grant acknowledge special cycle and the halt special cycle. The microprocessor executes the stop grant acknowledge special cycle in response to a request by the computer system to slow down its clock. This request is asserted by the computer system if the system has been idle for a predetermined period of time. The halt special cycle is generated by the microprocessor when a HALT instruction is executed. The stop grant acknowledge and halt special cycles place the microprocessor into a low power state. Since the microprocessor is in low power mode, the L2 cache memory is also placed into low power mode for further power conservation. The L2 cache memory is implemented either with synchronous or asynchronous static random access memories (SRAMs). To place a synchronous SRAM into low power mode, its address strobe input is asserted while its chip select input is deasserted. For an asynchronous SRAM, deasserting its chip select input causes the SRAM to transition into low power mode.

Abstract translation: 的电路被描述为放置在外部或L2高速缓存存储器进入低功耗模式，响应于由微处理器执行特殊的某些周期。 尤其特殊的周期可能是停批承认特殊周期和停止特殊循环。 微处理器执行的停止许可确认响应特殊周期的请求被计算机系统至其时钟放慢。 该请求由所述计算机系统断言如果系统已空闲了预定的时间段。 暂停周期特殊由微处理器当HALT指令被执行生成。 该停批承认并停止特殊周期中各微处理器进入低功耗状态。 由于微处理器处于低功率模式中，L2高速缓冲存储器被如此放置进入低功耗模式为节电此外。 在L2高速缓冲存储器被实现，也与同步或异步静态随机存取存储器（SRAM）。 放置一个同步SRAM进入低功耗模式，而它的片选输入被置为无效它的地址选通输入被断言。 的异步SRAM时，解除其芯片选择输入使SRAM转变到低功率模式。