公开(公告)号：EP0617365A1

公开(公告)日：1994-09-28

申请号：EP94302014.9

申请日：1994-03-22

Applicant: Compaq Computer Corporation

Inventor： Landry, John A. ,  Santeler, Paul A. ,  Thome, Gary W. ,  Bonella, Randy M. ,  Collins, Michael J.

IPC: G06F13/16

CPC classification number: G06F13/1615

Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller utilizes differing speed memory devices, such as 60 ns and 80 ns, on an individual basis, with each memory device operating at its full designed rate. The speed of the memory is stored for each 128 kbyte block of memory and used when the memory cycle is occurring to redirect a state machine, accomplishing a timing change of the memory devices.

Abstract translation: 一个内存控制器，最大限度地利用任何处理器流水线并同时运行大量的周期。 存储器控制器可以利用不同的速度存储器件并以其期望的最佳速度运行每个存储器件。 这些功能由多个简单的相互依赖的状态机执行，每个状态机负责整个操作的一小部分。 当每个状态机达到完成其功能时，它通知相关状态机现在可以继续进行，并继续等待下一个启动或继续指示。 下一台状态机以类似的方式运行。 负责一个周期的较早部分的状态机在下一个周期中开始执行任务，然后在负责周期的后期部分的状态机完成任务之前。 存储器控制器在逻辑上组织为三个主要块，前端块，存储块和主机块，每个都负责与其相关总线和组件的交互，并与各种其他块进行交互。 存储器控制器使用不同的速度存储器件，例如60ns和80ns，各个存储器件以其完全设计的速率工作。 存储器的速度是针对每个128K字节的存储器存储的，并且当发生存储器周期以重定向状态机时，使用该存储器的速度，从而实现存储器件的定时改变。

公开(公告)号：EP0886219A2

公开(公告)日：1998-12-23

申请号：EP98304744.0

申请日：1998-06-16

Applicant: Compaq Computer Corporation

Inventor： Santeler, Paul A. ,  Bacchus, Reza M. ,  Sabotta, Michael L.

IPC: G06F13/40

CPC classification number: G06F13/409

Abstract: The cage-supported hard disk drives in a computer server system are coupled to connectors on the cage back plane circuit boards and are controlled by a pair of array controller cards which are hot-plug connected in a redundant manner on the system I/O board using a pair of connectors mounted on the I/O board, each connector having first and second sets of electrical contacts thereon. Connector edge portions of the array controller cards are plugged into the I/O board connectors and have first and second sets of electrical contacts that engage the corresponding first and second sets of electrical contacts on their associated I/O board connectors. Formed on the I/O board are (1) a peripheral interconnect bus structure connected to the first sets of connector electrical contacts, (2) an electrical bus structure connected to the second sets of connector electrical contacts and associated cable connectors, and (3) an intercontroller bus structure connected between the second sets of connector electrical contacts and enabling the two array controller cards to communicate with one another independently of the peripheral interconnect bus structure. Electrical cables are interconnected between the electrical bus structure and the back plane circuit boards to couple the array controller cards thereto in a redundant control manner without requiring direct cable connection to either of the array controller cards.

Abstract translation: 计算机服务器系统中的笼支持的硬盘驱动器耦合到保持架背板电路板上的连接器，并由一对阵列控制器卡控制，这些阵列控制器卡以冗余方式热插拔连接到系统I / O板 使用安装在I / O板上的一对连接器，每个连接器在其上具有第一组和第二组电触点。 阵列控制器卡的连接器边缘部分插入到I / O板连接器中，并且具有与其相关联的I / O板连接器上的相应的第一组和第二组电触头相啮合的第一组和第二组电触头。 在I / O板上形成有（1）连接到第一组连接器电触头的外围互连总线结构，（2）连接到第二组连接器电触点和相关电缆连接器的电总线结构，（3） ）连接在所述第二组连接器电触点之间并且使得所述两个阵列控制器卡能够独立于所述外围互连总线结构彼此通信的互连控制器总线结构。 电气电缆在电气总线结构和背板电路板之间互连，以便以冗余的控制方式将阵列控制器卡耦合到其上，而不需要直接连接到任一阵列控制器卡。

公开(公告)号：EP0617366A1

公开(公告)日：1994-09-28

申请号：EP94302037.0

申请日：1994-03-22

Applicant: Compaq Computer Corporation

Inventor： Santeler, Paul A. ,  Thome, Gary W.

IPC: G06F13/16

CPC classification number: G06F9/3869 ,  G06F13/1615 ,  G06F13/1689

Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller utilizes different speed memory devices at each memory devices optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory system includes a single chip which provides all of the address and control signals to a memory device so that a clock cycle can be saved because of reduced skew of the signals. The signals are provided synchronously from the chip.

Abstract translation: 一种存储器控制器，其最大限度地利用任何处理器流水线的和同时运行大量循环的。 存储器控制器在每个存储器装置最佳速度利用不同速度的存储器装置。 功能是通过简单，相互依存的状态机的复数，每个负责整个操作的一个小部分上执行。 由于每个状态机到达已经完成它的功能，它会通知相关的状态机做到了，现在可以继续并继续等待它的下一个启动或进行指示。 接下来的状态机采用了类似的方式。 负责周期的早期部分的状态机已经在下一个周期开始了他们的任务，负责周期的后期部分的状态机已经完成了他们的任务之前。 所述存储器控制器被逻辑地组织为三个主要的块，前端块，存储块和主机块，每个负责与其相关的总线和部件和各种其它块为握手相互作用的相互作用。 该存储器系统包括一个单一的芯片，所有的地址和控制信号的提供到存储器设备，以便做一个时钟周期可以由于减少了信号的歪斜被保存。 的信号从芯片同步提供。

公开(公告)号：EP0617365B1

公开(公告)日：2001-06-13

申请号：EP94302014.9

申请日：1994-03-22

Applicant: Compaq Computer Corporation

Inventor： Landry, John A. ,  Santeler, Paul A. ,  Thome, Gary W. ,  Bonella, Randy M. ,  Collins, Michael J.

IPC: G06F13/16

CPC classification number: G06F13/1615

公开(公告)号：EP0886219A3

公开(公告)日：1999-12-15

申请号：EP98304744.0

申请日：1998-06-16

Applicant: Compaq Computer Corporation

Inventor： Santeler, Paul A. ,  Bacchus, Reza M. ,  Sabotta, Michael L.

IPC: G06F13/40

CPC classification number: G06F13/409

Abstract: The cage-supported hard disk drives in a computer server system are coupled to connectors on the cage back plane circuit boards and are controlled by a pair of array controller cards which are hot-plug connected in a redundant manner on the system I/O board using a pair of connectors mounted on the I/O board, each connector having first and second sets of electrical contacts thereon. Connector edge portions of the array controller cards are plugged into the I/O board connectors and have first and second sets of electrical contacts that engage the corresponding first and second sets of electrical contacts on their associated I/O board connectors. Formed on the I/O board are (1) a peripheral interconnect bus structure connected to the first sets of connector electrical contacts, (2) an electrical bus structure connected to the second sets of connector electrical contacts and associated cable connectors, and (3) an intercontroller bus structure connected between the second sets of connector electrical contacts and enabling the two array controller cards to communicate with one another independently of the peripheral interconnect bus structure. Electrical cables are interconnected between the electrical bus structure and the back plane circuit boards to couple the array controller cards thereto in a redundant control manner without requiring direct cable connection to either of the array controller cards.