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    Apparatus and method for positively and subtractively decoding addresses on a bus
    2.
    发明公开
    Apparatus and method for positively and subtractively decoding addresses on a bus 失效
    地址和邮件地址

    公开(公告)号：EP0820021A2

    公开(公告)日：1998-01-21

    申请号：EP97305239.2

    申请日：1997-07-15

    Applicant: Compaq Computer Corporation

    Inventor： Santos, Gregory N. ,  Maguire, David J. ,  Riley, Dwight D. ,  Edwards, James R.

    IPC: G06F13/40

    CPC classification number: G06F13/4045

    Abstract: A computer system having an expansion base for docking a portable portion of the computer system includes a bridge circuit for adaptively decoding addresses on a bus based on the docking status. Both the expansion base and the portable portion include the bridge circuit for passing cycles from a peripheral component interconnect (PCI) bus to an industry standard architecture (ISA) bus. The bridge includes internal devices and configuration registers for controlling the decoding. Bus cycles intended for internal devices and external devices connected to each respective ISA bus of the bridge circuits are positively decoded. Cycles not positively decoded and claimed are subtractively decoded by one of the bridge circuits depending on the docking status.

    Abstract translation: 具有用于对接计算机系统的便携式部分的扩展基座的计算机系统包括用于基于对接状态自适应地解码总线上的地址的桥接电路。 扩展基座和便携式部分都包括用于将周期从外围部件互连（PCI）总线传递到工业标准架构（ISA）总线的桥接电路。 该桥包括用于控制解码的内部设备和配置寄存器。 用于连接到桥接电路的每个相应ISA总线的内部设备和外部设备的总线周期被正确解码。 取决于对接状态，桥接电路之一由一个桥接电路进行减法解码和声明的循环。

    Circuit for handling distributed arbitration in a computer system having multiple arbiters
    3.
    发明公开
    Circuit for handling distributed arbitration in a computer system having multiple arbiters 失效
    Arbitrierungsverarbeitung电路，用于分布在具有多个仲裁器的计算机系统

    公开(公告)号：EP0820018A2

    公开(公告)日：1998-01-21

    申请号：EP97305238.4

    申请日：1997-07-15

    Applicant: Compaq Computer Corporation

    Inventor： Riley, Dwight D. ,  Edwards, James R. ,  Maguire, David J.

    IPC: G06F13/368 ,  G06F13/40

    CPC classification number: G06F13/368

    Abstract: An arbitration scheme for a computer system having multiple arbiters for arbitrating access to a plurality of buses. In the preferred embodiment, a computer system is divided into a detachable laptop portion and an expansion base unit coupled through a shared PCI bus. Each of the two portions of the computer system includes separate PCI arbitration circuitry for arbitrating requests for the PCI bus from potential PCI and ISA bus masters. Included within the laptop portion of the computer system is a top level arbiter that determines whether the PCI arbiter in the laptop or expansion base unit has access to the PCI bus. Either PCI arbiter normally must receive a grant from the top level arbiter before it runs a cycle. While the laptop computer is docked, the top level arbiter selects between the PCI arbiters on an essentially time multiplexed basis. While the expansion base and laptop computer are undocked, the top level arbiter grants bus access to the laptop PCI arbiter.

    Abstract translation: 对于具有用于仲裁到总线的多个接入的多个仲裁器的计算机系统中的仲裁方案。 在优选实施例中，一种计算机系统被分为可拆卸膝上型部分，并且通过共享的PCI总线连接扩展基础单元上。 每个计算机系统的两个部分包括用于仲裁来自潜在PCI和ISA总线主机的PCI总线请求独立的PCI仲裁电路。 包括在计算机系统的各部分的膝上型内是顶部级别仲裁器做确定性地雷无论是在笔记本电脑或扩展基础单元的PCI仲裁器有权访问PCI总线。 无论是PCI仲裁者运行循环开始前，通常必须得到顶级仲裁者的资助。 而这些笔记本电脑对接，顶部级别仲裁的仲裁器PCI间上基本上时分多路复用的基础上选择。 而扩张基部和膝上型计算机被出坞，顶部级别仲裁器准许的总线访问到笔记本PCI仲裁器。

    Interfacing direct memory access devices to a non-ISA bus
    4.
    发明公开
    Interfacing direct memory access devices to a non-ISA bus 失效
    施耐德电气公司

    公开(公告)号：EP0784277A1

    公开(公告)日：1997-07-16

    申请号：EP96308940.4

    申请日：1996-12-10

    Applicant: Compaq Computer Corporation

    Inventor： Wanner, Christopher C. ,  Stevens, Jeffrey C. ,  Lester, Robert A. ,  Riley, Dwight D. ,  Maguire, David J. ,  Edwards, James R.

    IPC: G06F13/28 ,  G06F13/12

    CPC classification number: G06F13/28 ,  G06F13/126

    Abstract: A computer system having separate, yet compatible DMA controllers on a bus. Each DMA controller for controlling at least one DMA channel, each DMA controller having an independent set of registers for performing DMA operations and a configuration register for indicating channel status and designation. A DMA master for compatibly communicating with a processor and for initializing and communicating with the multiple DMA controllers.

    Abstract translation: 一个计算机系统，在总线上具有独立但兼容的DMA控制器。 用于控制至少一个DMA通道的每个DMA控制器，每个DMA控制器具有用于执行DMA操作的独立的一组寄存器和用于指示通道状态和指定的配置寄存器。 DMA主机，用于与处理器进行兼容通信，并与多个DMA控制器进行初始化和通信。

    Circuit for handling distributed arbitration in a computer system having multiple arbiters
    7.
    发明公开
    Circuit for handling distributed arbitration in a computer system having multiple arbiters 失效
    Arbitrierungsverarbeitung电路，用于分布在具有多个仲裁器的计算机系统

    公开(公告)号：EP0820018A3

    公开(公告)日：1999-03-10

    申请号：EP97305238.4

    申请日：1997-07-15

    Applicant: Compaq Computer Corporation

    Inventor： Riley, Dwight D. ,  Edwards, James R. ,  Maguire, David J.

    IPC: G06F13/368 ,  G06F13/40

    CPC classification number: G06F13/368

    Abstract: An arbitration scheme for a computer system having multiple arbiters for arbitrating access to a plurality of buses. In the preferred embodiment, a computer system is divided into a detachable laptop portion and an expansion base unit coupled through a shared PCI bus. Each of the two portions of the computer system includes separate PCI arbitration circuitry for arbitrating requests for the PCI bus from potential PCI and ISA bus masters. Included within the laptop portion of the computer system is a top level arbiter that determines whether the PCI arbiter in the laptop or expansion base unit has access to the PCI bus. Either PCI arbiter normally must receive a grant from the top level arbiter before it runs a cycle. While the laptop computer is docked, the top level arbiter selects between the PCI arbiters on an essentially time multiplexed basis. While the expansion base and laptop computer are undocked, the top level arbiter grants bus access to the laptop PCI arbiter.

    Computer system incorporating hot docking and undocking capabilities without requiring a standby or suspend mode
    10.
    发明公开
    Computer system incorporating hot docking and undocking capabilities without requiring a standby or suspend mode 失效
    计算机系统与源附加去除解决方案，而降噪模式或维护模式

    公开(公告)号：EP0820022A3

    公开(公告)日：1999-02-03

    申请号：EP97305240.0

    申请日：1997-07-15

    Applicant: Compaq Computer Corporation

    Inventor： Lin, Richard S. ,  Maguire, David J. ,  Edwards, James R. ,  Delisle, David J.

    IPC: G06F13/40

    CPC classification number: G06F13/4081 ,  G06F13/36

    Abstract: A method for hot docking and hot undocking a portable computer and a docking station. The portable computer and docking station are physically coupled via a shared PCI bus and an expansion connector. Varying length pins in the expansion connector generate docking and undocking handshaking signals used by microcontrollers in the portable computer and docking station. The portable computer and docking station are functionally connected via low on-resistance switches located in the portable computer. Following a docking event, closure of the switches connects the portion of the shared PCI bus in the docking station with the PCI bus in the portable computer. When the switches are open, the PCI busses are functionally isolated. Both the portable computer and the docking station also include a local arbiter for arbitrating and granting bus control requests from devices coupled to the shared PCI bus. These local arbiters may be placed into an idled state by either the operating system (through system BIOS) or by the microcontrollers. The arbiters are idled during docking and undocking events in order to inhibit bus cycles on the PCI bus, thereby preventing cycles from being lost. Following completion of a hot docking or undocking event, Plug-and-Play system reconfiguration is carried out so that all system resources may be recognized and properly utilized by the operating system.

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