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    3.
    发明专利
    未知

    公开(公告)号：DE60025697D1

    公开(公告)日：2006-04-13

    申请号：DE60025697

    申请日：2000-02-08

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO ,  MONTANARO MASSIMO ,  ODDONE GIORGIO

    IPC: H02M3/07

    Abstract: A voltage boosting device for speeding power-up of multilevel nonvolatile memories, including a voltage regulator (11) and a charge pump (13) and having an output terminal (10); the voltage regulator (11) having a regulation terminal connected to the output terminal (10), and an output (16) supplying a control voltage (VL); the read charge pump (13) having an output connected to the output terminal (10) and supplying a read voltage (VR). The device further includes an enable circuit (12) connected to the output (16) and having a pump enable output (17) connected to a charge pump enable terminal (13) and supplying a pump enable signal (PE). The pump enable signal (PE) is set at a first logic level so as to activate the charge pump (13) when the read voltage (VR) is lower than a nominal value. In addition, the device generates a power-up sync signal (ATDS) which activates a read operation when the read voltage (VR) reaches its nominal value and a chip enable signal (CE) is set at an active value.

    4.
    发明专利
    未知

    公开(公告)号：DE60039587D1

    公开(公告)日：2008-09-04

    申请号：DE60039587

    申请日：2000-05-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO ,  MONTANARO MASSIMO ,  ODDONE GIORGIO

    IPC: G11C11/56 ,  G11C16/28

    Abstract: The invention relates to a circuit structure (1) for programming data in reference cells (3) of an electrically programmable/erasable integrated non-volatile memory device, comprising a matrix of multi-level memory cells and at least one corresponding reference cell provided for comparison with a respective memory cell during the read phase. The reference cell (3) is incorporated, along with other cells of the same type, to a reference cell sub-matrix (4) which is structurally independent of the memory cell matrix and directly accessed from outside in the DMA mode. The bit lines of the sub-matrix (4) branch off to a series of switches (9) which are individually operated by respective control signals REF(i) issued from a logic circuit (8) with the purpose of selectively connecting the bit lines to a single external I/O terminal (10) through a single addressing line (11) of the access DMA mode.

    5.
    发明专利
    未知

    公开(公告)号：DE60039027D1

    公开(公告)日：2008-07-10

    申请号：DE60039027

    申请日：2000-03-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO ,  MONTANARO MASSIMO ,  ODDONE GIORGIO

    IPC: G11C16/12

    Abstract: The integrated device (100) comprises a PMOS transistor (101) and a voltage selector (1) having an output (6g) connected to the bulk terminal (101d) of the PMOS transistor (101). The voltage selector (1) comprises an input stage (2) supplying (2c) a supply voltage (Vdd) or a programming voltage (Vpp) according to whether the device (100) is in a reading step or in a programming step; a comparator (3) connected to the output (2c) of the input stage (2), receiving a boosted voltage (Vboost), and generating (3g) a first control signal (OC), the state whereof depends upon the comparison of the voltages at the inputs of the comparator (3); a logic circuit (4) connected to the output (3g) of the comparator (3) and generating a second control signal (VDDIS), the state whereof depends upon the state of the first control signal (OC) and of a third-level signal (VTL); and a switching circuit (6) controlled by the first control signal (OC), by the second control signal (VDDIS), and by the third-level signal (VTL) and supplying (6g) each time the highest among the supply voltage (Vdd), the boosted voltage (Vboost), and the programming voltage (Vpp).

    8.
    发明专利
    未知

    公开(公告)号：DE60037504T2

    公开(公告)日：2008-12-11

    申请号：DE60037504

    申请日：2000-05-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO ,  MONTANARO MASSIMO ,  ODDONE GIORGIO

    IPC: G11C16/28 ,  G11C11/56

    Abstract: The invention relates to a circuit structure (1) for reading data contained in an electrically programmable/erasable integrated non-volatile memory device, comprising a matrix (2) of memory cells (3) and at least one reference cell (4) for comparison with a memory cell (3) during a reading phase. The reference cell (4) is incorporated in a reference cells sub-matrix (5) which is structurally independent of the matrix (2) of memory cells (3). Also provided is a conduction path between the matrix (2) and the sub-matrix (5), which path includes bit lines (b1ref) of the submatrix (5) of reference cells (4) extended continuously into the matrix (2) of memory cells (3)

    9.
    发明专利
    未知

    公开(公告)号：ITTO20010537D0

    公开(公告)日：2001-06-05

    申请号：ITTO20010537

    申请日：2001-06-05

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FONTANA MARCO ,  PAGLIATO MAURO ,  ROLANDO PAOLO ,  ODDONE GIORGIO

    IPC: H02M3/07

    Abstract: The voltage applied to the gate terminals of the charging transistors and charge-transfer transistors of two parallel pumping branches forming a charge pump is a boosted voltage generated internally and supplied in a crosswise manner. In particular, for driving the charge pump, first and second driving signals are generated respectively for the first and for the second pumping branch via a first and respectively a second driving circuit; the first and second driving signals are also supplied respectively to a first and to a second auxiliary charge pump to obtain respectively first and second voltage-boosted signals; and the first and second boosted voltages are respectively supplied to the second and to the first driving circuit.

    10.
    发明专利
    未知

    公开(公告)号：DE60037504D1

    公开(公告)日：2008-01-31

    申请号：DE60037504

    申请日：2000-05-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO ,  MONTANARO MASSIMO ,  ODDONE GIORGIO

    IPC: G11C16/28 ,  G11C11/56

    Abstract: The invention relates to a circuit structure (1) for reading data contained in an electrically programmable/erasable integrated non-volatile memory device, comprising a matrix (2) of memory cells (3) and at least one reference cell (4) for comparison with a memory cell (3) during a reading phase. The reference cell (4) is incorporated in a reference cells sub-matrix (5) which is structurally independent of the matrix (2) of memory cells (3). Also provided is a conduction path between the matrix (2) and the sub-matrix (5), which path includes bit lines (b1ref) of the submatrix (5) of reference cells (4) extended continuously into the matrix (2) of memory cells (3)

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