Abstract:
An improved thermal interface material for conducting heat away from an integrated circuit device into a heat sink is a composite material including a metal screen defining openings and a hardened structural bonding agent incorporated into the openings of the metal screen. The improved composite thermal interface material achieves outstanding bonding properties superior to conventional thermal interface materials, while also exhibiting exceptional thermal conductivity.
Abstract:
An electronics assembly (10) is provided having a substrate (12) and at least one electronics package (20) supported on the substrate (12). The electronics package (20) also has electrical circuitry and first and second side surfaces. The assembly (10) further includes a first heat sink device (30) positioned in thermal communication with the first side surface of the electronics package (20), and a second heat sink device (40) positioned in thermal communication with the second side surface of the electronics package (20).
Abstract:
A method that employs a novel combination of conventional fabrication techniques provides a ceramic short-resistant capacitor (30) that is bendable and/or shapeable to provide a multiple layer capacitor that is extremely compact and amenable to desirable geometries. The method allows thinner and more flexible ceramic capacitors to be made. The method includes forming a first thin metal layer (12) on a substrate (10); depositing a thin, ceramic dielectric layer (14) over the metal layer (12); depositing a second thin metal layer (18) over the dielectric layer to form a capacitor exhibiting a benign failure mode; and separating the capacitor (30) from the substrate (10).
Abstract:
A capacitor (10) exhibiting a benign failure mode has a first electrode layer (12), a first ceramic dielectric layer (14) deposited on a surface of the first electrode (12), and a second electrode layer (16) disposed on the ceramic dielectric layer (14), wherein selected areas of the ceramic dielectric layer (14) have additional dielectric material (18) of sufficient thickness to exhibit a higher dielectric breakdown voltage than the remaining majority of the dielectric layer (14). The added thickness of the dielectric layer (14) in selected areas allows lead connections (22) to be made at the selected areas of greater dielectric thickness while substantially eliminating a risk of dielectric breakdown and failure at the lead connections (22), whereby the benign failure mode is preserved.
Abstract:
A capacitor (10) exhibiting a benign failure mode has a first electrode layer (12), a first ceramic dielectric layer (14) deposited on a surface of the first electrode (12), and a second electrode layer (16) disposed on the ceramic dielectric layer (14), wherein selected areas of the ceramic dielectric layer (14) have additional dielectric material (18) of sufficient thickness to exhibit a higher dielectric breakdown voltage than the remaining majority of the dielectric layer (14). The added thickness of the dielectric layer (14) in selected areas allows lead connections (22) to be made at the selected areas of greater dielectric thickness while substantially eliminating a risk of dielectric breakdown and failure at the lead connections (22), whereby the benign failure mode is preserved.
Abstract:
A multi-layer capacitor (10) includes an anode (12), a cathode (16), a dielectric material (20), a first endcap (22A), and a second endcap (22B). The anode (12) and cathode (16) are formed of one or more layers (14A, 14B) of interlaced conductive material. The dielectric material (20) is interposed between each of the layers (14A, 14B) of the anode (12) and the cathode (16). The first and second endcaps configured to interconnect each of the layers (14A, 14B) of the anode (12) and cathode (16), respectively. The endcaps are formed of conductive nano material. A method of forming an endcap of a capacitor (10) configured to interconnect one or more layers (14A, 14B) of conductive material includes the step of applying conductive nano material (34) to exposed conductive surfaces of at least one of an anode (12) and a cathode (16) of the one or more layers (14A, 14B) of conductive material. The method also includes the step of exposing the nano material to a source of energy effective to initiate self-sintering of the nano material.
Abstract:
A lead-lanthanum-zirconium-titanate (PLZT) capacitor (10) on a substrate (12) formed of an inorganic film glass. The first metallization layer (14) is deposited on a top side of the substrate (12) to form a first electrode (18). The dielectric layer (20) of PLZT is deposited over the first metallization layer (14). The second metallization layer (22) deposited over the dielectric layer (20) to form a second electrode (24). The glass substrate (12) is advantageous as glass is compatible with an annealing process at 650°C used to form the capacitor (10). Further, the inorganic glass film capacitor (10) can be roll to form a wound capacitor with increased electrical properties.
Abstract:
A lead-lanthanum-zirconium-titanate (PLZT) capacitor (10) on a substrate (12) formed of an inorganic film glass. The first metallization layer (14) is deposited on a top side of the substrate (12) to form a first electrode (18). The dielectric layer (20) of PLZT is deposited over the first metallization layer (14). The second metallization layer (22) deposited over the dielectric layer (20) to form a second electrode (24). The glass substrate (12) is advantageous as glass is compatible with an annealing process at 650°C used to form the capacitor (10). Further, the inorganic glass film capacitor (10) can be roll to form a wound capacitor with increased electrical properties.