公开(公告)号：WO2004051745A3

公开(公告)日：2005-02-24

申请号：PCT/DE0303769

申请日：2003-11-13

Applicant: EPCOS AG ,  BAUERNSCHMITT ULRICH ,  MEISTER VEIT

Inventor： BAUERNSCHMITT ULRICH ,  MEISTER VEIT

IPC: H01L21/50 ,  H01L23/10 ,  H01L23/522 ,  H01L23/552 ,  B81B7/00 ,  H01L23/04 ,  H01L23/31 ,  H01L25/065 ,  H01L25/16 ,  H03H3/08 ,  H03H9/05

CPC classification number: B81C1/0023 ,  H01L21/50 ,  H01L23/10 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/5222 ,  H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/15192 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2924/30107 ,  H03H9/0542 ,  H03H9/10 ,  H03H9/1057 ,  H03H9/1078 ,  H03H9/1085 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention relates to an electronic component comprising a plurality of chips (CH1, CH2) which are arranged on a base plate (BP) and are electrically connected to the same by means of various connection techniques e.g. the flip-chip technique, surface mounted design or the wire bonding technique. The invention also relates to an encapsulation of the chips (individually or in groups of at least two chips) with a covering element (AB), and a corresponding production method.

Abstract translation: 本发明涉及一种具有多个布置在基板（BP）芯片（CH1，CH2）的电子部件，并与通过不同的技术，这样的装置，该化合物。 作为倒装芯片技术，表面安装设计或引线接合技术电连接。 本发明提出的芯片（单独地或作为一组至少两个芯片的）与盖（AB）和用于生产它们的方法的封装。

公开(公告)号：WO2008142081A9

公开(公告)日：2009-04-23

申请号：PCT/EP2008056200

申请日：2008-05-20

Applicant: EPCOS AG ,  MAIER MARTIN ,  OBESSER MICHAEL ,  KASTNER KONRAD ,  PORTMANN JUERGEN ,  BAUERNSCHMITT ULRICH

Inventor： MAIER MARTIN ,  OBESSER MICHAEL ,  KASTNER KONRAD ,  PORTMANN JUERGEN ,  BAUERNSCHMITT ULRICH

IPC: H01L23/485

CPC classification number: H01L24/05 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/0236 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2924/01005 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01061 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1461 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention relates to a component with multi-layered connection surfaces that can be soldered or bonded to a substrate (SU). Said component has, in addition to the electrically conductive pad metallisation (PM) and the UBM-metallisation (UBM), an electrically conductive stress compensation layer (SK) that is arranged between the substrate and pad-metallisation or between the pad-metallisation and the UBM-metallisation. The stress insensitivity of the connection metallisation is obtained by a stress compensation layer, the E-module thereof being lower than that of the UBM-metallisation.

Abstract translation: 它提出了一种基底（SU），在具有多层可焊接或粘合的衬垫的装置，其除了所述导电焊盘金属（PM）和UBM金属化（UBM）另外的导电应力补偿层（SK），则 在衬底和焊盘金属化之间或焊盘金属化和UBM金属化之间布置。 端子金属化的应力不敏感性通过其E模块低于UBM金属化的应力补偿层来实现。

公开(公告)号：WO2008142081A3

公开(公告)日：2009-03-05

申请号：PCT/EP2008056200

申请日：2008-05-20

Applicant: EPCOS AG ,  MAIER MARTIN ,  OBESSER MICHAEL ,  KASTNER KONRAD ,  PORTMANN JUERGEN ,  BAUERNSCHMITT ULRICH

Inventor： MAIER MARTIN ,  OBESSER MICHAEL ,  KASTNER KONRAD ,  PORTMANN JUERGEN ,  BAUERNSCHMITT ULRICH

IPC: H01L23/485

CPC classification number: H01L24/05 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/0236 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2924/01005 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01061 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1461 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention relates to a component with multi-layered connection surfaces that can be soldered or bonded to a substrate (SU). Said component has, in addition to the electrically conductive pad metallisation (PM) and the UBM-metallisation (UBM), an electrically conductive stress compensation layer (SK) that is arranged between the substrate and pad-metallisation or between the pad-metallisation and the UBM-metallisation. The stress insensitivity of the connection metallisation is obtained by a stress compensation layer, the E-module thereof being lower than that of the UBM-metallisation.

Abstract translation: 它提出了一种基底（SU），在具有多层可焊接或粘合的衬垫的装置，其除了所述导电焊盘金属（PM）和UBM金属化（UBM）另外的导电应力补偿层（SK），则 设置在基板和焊盘金属之间或焊盘金属化和UBM之间的金属化。 连接金属化的应力不敏感由应力补偿层，其模量比UBM金属化下实现的。

公开(公告)号：CA2294167A1

公开(公告)日：1998-12-17

申请号：CA2294167

申请日：1998-06-03

Applicant: EPCOS AG

Inventor： BAIER THOMAS ,  BAUERNSCHMITT ULRICH

IPC: H03H9/145 ,  H03H9/64

Abstract: The invention relates to a transversal-mode resonator filter with reflectors (R1, R3) and input and output transformers (W1, W2) arranged between said reflectors. The impedance of the input and/or output transformers is adjusted by reducing the original active finger overlapping of the normal finger structure. The amount of reduction can vary when the finger overlapping of the transformers is reduced.

公开(公告)号：DE59805424D1

公开(公告)日：2002-10-10

申请号：DE59805424

申请日：1998-06-03

Applicant: EPCOS AG

Inventor： BAIER THOMAS ,  BAUERNSCHMITT ULRICH

IPC: H03H9/145 ,  H03H9/64

公开(公告)号：CA2325434A1

公开(公告)日：1999-09-30

申请号：CA2325434

申请日：1999-03-22

Applicant: EPCOS AG

Inventor： JOHANNES THOMAS ,  BAIER THOMAS ,  BAUERNSCHMITT ULRICH ,  ROSLER ULRIKE ,  ALI-HACKL MARKUS ,  FREISLEBEN STEFAN

IPC: H03H9/145 ,  H03H9/00 ,  H03H9/02 ,  H03H9/64

Abstract: The present invention relates to a surface-wave acoustic filter having a capacitive and inductive cross-talk which is compensated between adjacent and interdigitated input and output transformers. These transformers (20; 23) are divided into partial transformers (d, d'; e, e') and the guidance of their pads (24, 25; 26, 27) is modified so that the magnetic couplings between adjacent partial transformers have opposite flow directions (H, H') and so that the total magnetic flow induced is equal to zero. The partial transformers are mounted in series or in parallel so that during a symmetrical operation, the cross-talk capacities between adjacent pads and transformer surfaces are compensated at the corresponding gate.

公开(公告)号：DE102007023590A1

公开(公告)日：2008-11-27

申请号：DE102007023590

申请日：2007-05-21

Applicant: EPCOS AG

Inventor： MAIER MARTIN ,  KASTNER KONRAD ,  OBESSER MICHAEL ,  PORTMANN JUERGEN ,  BAUERNSCHMITT ULRICH

IPC: H01L23/482

公开(公告)号：DE59913935D1

公开(公告)日：2006-11-30

申请号：DE59913935

申请日：1999-03-22

Applicant: EPCOS AG

Inventor： ALI-HACKL MARKUS ,  FREISLEBEN STEFAN ,  JOHANNES THOMAS ,  BAIER THOMAS ,  BAUERNSCHMITT ULRICH ,  ROESLER ULRIKE

IPC: H03H9/145 ,  H03H9/64 ,  H03H9/00 ,  H03H9/02

Abstract: A surface acoustic wave filter having compensated capacitive and inductive crosstalk between adjacent IDT input and output transducers includes electromagnetically coupled transducers split into partial transducers. The routing of the partial transducer pads is modified such that the flux directions of the magnetic couplings between the adjacent partial transducers are oppositely directed so that the total induced magnetic flux is zero. The partial transducers are connected in series or in parallel such that, in the case of symmetric operation, the crosstalk capacitances between adjacent pads and transducer surfaces are balanced at the corresponding port.

公开(公告)号：DE19900326A1

公开(公告)日：2000-11-23

申请号：DE19900326

申请日：1999-01-07

Applicant: EPCOS AG

Inventor： BAUERNSCHMITT ULRICH ,  EDER CLAUDIA

IPC: H03H9/145 ,  H03H9/64

Abstract: The filter arrangement is implemented on a chip and contains an input region (E) with one or more electrically parallel transversal mode resonator or TMR input filters (EA,EB) and an output region (A) with one or more parallel TMR output filters. The input and output regions are electrically connected in series via a coupling point (K) and have different numbers of filters. The input impedance differs from the output impedance. Active finger overlap of at least one resonator (R2EA,R1EB) adjacent to the coupling point and associated with one of the TMR filters is reduced for impedance matching at the coupling point

公开(公告)号：DE102008020783A1

公开(公告)日：2009-10-29

申请号：DE102008020783

申请日：2008-04-25

Applicant: EPCOS AG

Inventor： FREISLEBEN STEFAN ,  HOFMANN MIRA ,  MAIER MARTIN ,  BAUERNSCHMITT ULRICH

IPC: H03H9/64