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    ELECTRIC COMPONENT WITH A FLIP-CHIP CONSTRUCTION
    1.
    发明申请
    ELECTRIC COMPONENT WITH A FLIP-CHIP CONSTRUCTION 审中-公开
    电气元件进行倒装片设计

    公开(公告)号：WO2006015642A3

    公开(公告)日：2006-09-08

    申请号：PCT/EP2005006165

    申请日：2005-06-08

    Applicant: EPCOS AG ,  KRUEGER HANS ,  NICOLAUS KARL ,  PORTMANN JUERGEN ,  SELMEIER PETER

    Inventor： KRUEGER HANS ,  NICOLAUS KARL ,  PORTMANN JUERGEN ,  SELMEIER PETER

    IPC: H01L21/60

    CPC classification number: H01L23/49838 ,  H01L23/50 ,  H01L23/562 ,  H01L24/14 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/10135 ,  H01L2224/14132 ,  H01L2224/81136 ,  H01L2224/81139 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2224/29099 ,  H01L2224/05599

    Abstract: The invention relates to an electric component comprising a carrier substrate (1), which has a thermal expansion coefficient a p and a chip (2), which is fixed onto the carrier substrate (1) in a flip-chip construction by means of bumps (31 to 34). In a preferred orientation x 1 , the chip (2) has a thermal expansion co-efficient a 1 , whereby ?a 1 = |a p - a 1 | represents the first expansion differential. In a second preferred orientation x 2 , the chip (2) has a thermal expansion coefficient a 2 , whereby ?a 2 = |a p - a 2 | represents the second expansion differential. ?x 1 is the distance between the centres (310, 320) of the terminal bumps (31, 32) in the x 1 orientation. ?x 2 is the distance between the centres (330, 340) of the terminal bumps (33, 34) in the x 2 orientation. The following applies: ?x 1 2 when ?ax 1 > ?a 2 and ?x 1 > ?x 2 when ?a 1 2 . This enables the shear force that occurs during temperature modifications and that acts on the terminal bumps to be minimised.

    Abstract translation: 本发明涉及一种包含（1）具有的热膨胀系数的p载体衬底的电子组件，和一个芯片（2），其是（1）安装在倒装芯片型通过凸块（31〜34）的方式在载体衬底上。 该芯片（2）具有在第一个优选的方向x 1 的热膨胀系数的 1 ，其中 1 = | AP - 一个< SUB> 1 | 第一膨胀差。 该芯片（2）具有在第二个优选的方向x 2 的热膨胀系数的 2 ，其中 2 = | AP - 一个< SUB> 2 | 第二膨胀差。 ？X 1 是在x方向上 1 端子凸块（31，32）的中心（310，320）之间的距离。 ？X 2 是在x方向上 2 端子凸块（33，34）的中心（330，340）之间的距离。 其中 2 ？在？斧 1 >真？X 1 ？A 2 和βX 1 <在/ SUB >>？X 2 ？一个 1 <？A 2 。 从而可以最小化在温度产生的变化以及作用在终端凸点的剪切力是可能的。

    METHOD FOR PRODUCING A SENSOR
    2.
    发明申请
    METHOD FOR PRODUCING A SENSOR 审中-公开
    生产传感器的方法

    公开(公告)号：WO2013124170A2

    公开(公告)日：2013-08-29

    申请号：PCT/EP2013052553

    申请日：2013-02-08

    Applicant: EPCOS AG

    Inventor： PAHL WOLFGANG ,  LEIDL ANTON ,  PORTMANN JUERGEN ,  EICHINGER ROBERT ,  SIEGEL CHRISTIAN ,  NICOLAUS KARL ,  WASSNER THOMAS ,  SEDLMEIER THOMAS

    IPC: B81C1/00

    CPC classification number: B81C1/00333 ,  B81C99/0045 ,  H01L22/12 ,  H01L2224/16225 ,  H01L2924/1461 ,  H04R31/006 ,  H01L2924/00

    Abstract: The invention relates to a method for producing a sensor (SEN), comprising the steps of arranging a sensor element (SE) on a carrier (TR), arranging a cover (AF) on the sensor element (SE), wherein the sensor element (SE) is enclosed between the cover (AF) and the carrier (TR), adhering a carrier film (TF) to the cover (AF), and producing an opening (SO) in the carrier film (TF) and the cover (AF), wherein the openings (SO) in the carrier film (TF) and the cover (AF) at least partially overlap.

    Abstract translation: 本发明涉及一种方法，用于制造传感器（SEN），其包含载体（TR）上定位的传感器元件（SE），所述传感器元件（SE）上配置覆盖物（AF），的步骤，其中的传感器元件（SE） 将背衬片（TF）粘附到盖（AF），并且在背衬片（TF）和盖（AF）中形成开口（SO），开口 （SO）在载体膜（TF）和盖（AF）中至少部分重叠。

    5.
    发明专利
    未知

    公开(公告)号：DE102008025202A1

    公开(公告)日：2009-12-10

    申请号：DE102008025202

    申请日：2008-05-27

    Applicant: EPCOS AG

    Inventor： BAUER CHRISTIAN ,  KRUEGER HANS ,  PORTMANN JUERGEN ,  STELZL ALOIS

    IPC: H01L23/02 ,  B81B7/02 ,  B81C1/00 ,  H03H9/10

    Abstract: Frames (3) applied on a wafer (1) are leveled and covered with a covering film, such that gas-tight housings are formed for component structures (5), in particular for filter or MEMS structures. Inner columns (4) can be provided for supporting the housing and for the ground connection; outer columns (4) can be provided for the electrical connection and are connected to the component structures by means of conductor tracks (6) that are electrically insulated from the frames (3).

    6.
    发明专利
    未知

    公开(公告)号：DE10238523A1

    公开(公告)日：2004-03-04

    申请号：DE10238523

    申请日：2002-08-22

    Applicant: EPCOS AG

    Inventor： FEIERTAG GREGOR ,  STELZL ALOIS ,  KRUEGER HANS ,  PORTMANN JUERGEN ,  NICOLAUS KARL

    IPC: H01L23/02 ,  H01L29/06 ,  H03H3/08 ,  H03H9/05 ,  H03H9/10 ,  H03H9/25 ,  H01L23/485 ,  H01L23/28 ,  H01L21/52 ,  H03H9/145

    Abstract: The present invention relates to an encapsulated component that includes a carrier substrate and at least one chip positioned on the top of the carrier substrate and electrically connected to it by means of electrically conductive connections. The encapsulation of the chip is accomplished with a seal or dielectric layer. As a result of differing coefficients of expansion of the seal or dielectric layer and the electrically conductive connections, with changing temperatures stresses occur in the electrically conductive connections, which can lead to cracks, breaks and even to interruption of the electrically conductive connections. To mechanically relieve the electrically conductive connections of stresses from changing temperatures (in particular under extreme thermal loads), it is proposed that the carrier substrate be provided with a support element that encircles the chip, which serves to support the seal or dielectric layer, and/or that the material and the arrangement of the encapsulation be selected accordingly.

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