Abstract:
The invention relates to a metallization (40) (and a semiconductor wafer (10) having corresponding metallization) and to a method for the production thereof that first of all can be produced by means of physical gas phase separation (dry separation) and secondly ensures sufficient adhesion of a lot bump. The method for producing a metallization (40) for at least one contact pad (20) according to the invention comprises the following process steps: applying at least one contact pad (20) to a substrate (10), applying a barrier layer (30) to the top side of the at least one contact pad (20) and applying a metallization (40) to the top side of the barrier layer (30), the barrier layer (30) and the metallization (40) being applied by means of physical separation and the metallization (40) being designed as a layer structure having two multiple alternating metallization layers (41, 42), wherein the first metallization layer (41) is made of nickel or an Ni alloy having a layer thickness of less than 500 nm and the second metallization layer (42) is made of a material that is different than nickel and is electrically conductive.
Abstract:
The invention relates to a method for producing vertical electrical connections (micro-vias) in semiconductor wafers for the fabrication of semiconductor components. The method is characterized by the following steps: - application of a protective resist to the wafer front side - patterning of the protective resist on the wafer front side such that the contacts to be connected to the wafer rear side become free - laser drilling of passage holes at the contact connection locations from the wafer rear side through the semiconductor substrate, the active layers and the contacts to be connected on the wafer front side - cleaning of the wafer (debris removal) - application of a plating base to the wafer rear side and into the laser-drilled passage holes - application of gold by electrodeposition onto the metallized wafer rear side and the passage holes - resist stripping of the protective resist - application of an antiwetting layer in the region of the entrance openings of the passage holes at the wafer rear side.
Abstract:
The invention relates to a method for producing vertical through-contacts (micro-vias) in semi-conductor wafers in order to produce semi-conductor components, i.e. contacts on the front side of the wafer through the semi-conductor wafer to the rear side of the wafer. The invention also relates to a method which comprises the following steps: blind holes on the contact connection points are laser drilled from the rear side of the wafer into the semi-conductor substrate, the wafer is cleaned, the semi-conductor substrate is plasma etched in a material selected manner until the active layer stack of the wafer is reached, the active layer stack of the wafer is plasma etched in a material selective manner until the contacts, which are to be connected to the rear side of the wafer, are reached, a plating base is applied to the rear side of the wafer and into the blind holes and gold is applied by electrodeposition onto the metallizied rear side of the wafer and the blind holes.
Abstract:
The method involves applying a protective resist on a silicon carbide wafer (1) front side and laser boring of passage holes through the wafer and active layers at contact connection locations of the wafer-rear side. The wafer is cleaned, and a plating base is applied on the wafer-rear side and into the laser-drilled holes. Gold is galvanically applied on the wafer-rear side and the holes. An antiwetting layer (8) is applied in an area of entrance openings of the holes at the wafer-rear side, where the layer comprises titanium.
Abstract:
The method involves coating contact surfaces, active layer surface and heat dissipation surfaces of microchips, with gold-tin-solder in a thickness which is greater than planar difference of a gold layer of the chips. The surfaces of the microchips correspond to the contact surfaces and the active layer surface. The chips are soldered by heating of the arrangement along with the substrate. An independent claim is also included for an electronic component comprising a microchip mounted on a carrier.
Abstract:
Procedimiento para la producción de una metalización (40) para al menos una almohadilla de contacto (20) con las siguientes etapas de procedimiento: - aplicar al menos una almohadilla de contacto (20) a una oblea semiconductora (10), - aplicar una capa de barrera (30) al lado superior de la al menos una almohadilla de contacto (20), - aplicar una metalización (40) al lado superior de la capa de barrera (30), configurándose la metalización (40) como estructura de capas de dos capas de metalización de alternancia múltiple (41, 42), configurándose la primera capa de metalización (41) de níquel con un grosor de capa de menos de 100 nm y la segunda capa de metalización (42) con un espesor de capa de entre 30 nm y 50 nm; caracterizado porque la capa de barrera (30) y la metalización (40) se aplican por medio de deposición física en fase de vapor, la segunda capa de metalización (42) se configura de oro y la suma de los grosores de capa de las primeras capas de metalización (41) es de más de 1 μm.
Abstract:
Die vorliegende Erfindung betrifft ein Verfahren zur Herstellung einer Metallisierung für mindestens ein Kontaktpad und einen Halbleiterwafer mit Metallisierung für mindestens ein Kontaktpad. Es ist Aufgabe der vorliegenden Erfindung, eine Metallisierung (bzw. einen Halbleiterwafer mit entsprechender Metallisierung) und ein Verfahren zu deren Herstellung anzugeben, die einerseits mittels physikalischer Gasphasenabscheidung (Trockenabscheidung) herstellbar sind und andererseits eine ausreichend hohe Adhäsion eines Lot-Bumps gewährleisten. Das erfindungsgemäße Verfahren zur Herstellung einer Metallisierung (40) für mindestens ein Kontaktpad (20) weist folgende Verfahrensschritte auf: Aufbringen mindestens eines Kontaktpads (20) auf ein Substrat (10), Aufbringen einer Barriereschicht (30) auf die Oberseite des mindestens einen Kontaktpads (20), und Aufbringen einer Metallisierung (40) auf die Oberseite der Barriereschicht (30), dadurch gekennzeichnet, dass die Barriereschicht (30) und die Metallisierung (40) mittels physikalischer Abscheidung aufgebracht werden und dass die Metallisierung (40) als Schichtstruktur zweier, mehrfach alternierender Metallisierungsschichten (41, 42) ausgebildet wird, wobei die erste Metallisierungsschicht (41) aus Nickel oder einer Ni-Legierung mit einer Schichtdicke kleiner als 500 nm und die zweite Metallisierungsschicht (42) aus einem von Nickel verschiedenen, elektrisch leitfähigen Material ausgebildet wird.