Abstract:
A semiconductor device is presented. The device includes a semiconductor layer including silicon carbide, and having a first surface and a second surface. A gate insulating layer is disposed on a portion of the first surface of the semiconductor layer, and a gate electrode is disposed on the gate insulating layer. The device further includes an oxide disposed between the gate insulating layer and the gate electrode at a corner adjacent an edge of the gate electrode so as the gate insulating layer has a greater thickness at the corner than a thickness at a center of the layer. A method for fabricating the device is also provided.
Abstract:
A semiconductor device is presented. The device includes a semiconductor layer including silicon carbide, and having a first surface and a second surface. A gate insulating layer is disposed on a portion of the first surface of the semiconductor layer, and a gate electrode is disposed on the gate insulating layer. The device further includes an oxide disposed between the gate insulating layer and the gate electrode at a corner adjacent an edge of the gate electrode so as the gate insulating layer has a greater thickness at the corner than a thickness at a center of the layer. A method for fabricating the device is also provided.
Abstract:
A silicon carbide device is presented that includes a gate electrode disposed over a portion of a silicon carbide substrate as well as a dielectric film disposed over the gate electrode. The device has a contact region disposed near the gate electrode and has a layer disposed over the dielectric film and over the contact region. The layer includes nickel in portions disposed over the dielectric film and includes nickel silicide in portions disposed over the contact region. The nickel silicide layer is configured to provide an ohmic contact to the contact region of the silicon carbide device.
Abstract:
Ein Verfahren, zu dem die Schritte gehören: Einbringen einer Dotierungssubstanz in eine Halbleiterschicht, um ein Vertiefungsgebiet der Halbleiterschicht zu bilden, wobei das Vertiefungsgebiet ein Kanalgebiet aufweist; und Einbringen einer Dotierungssubstanz in das Vertiefungsgebiet, um ein mehrfach implantiertes Gebiet zu bilden, das im Wesentlichen mit dem Vertiefungsgebiet übereinstimmt, jedoch das Kanalgebiet ausschließt.
Abstract:
A semiconductor device (200) is provided and includes a substrate (202) comprising silicon carbide; a drift layer (214) disposed over the substrate and comprising a drift region (214) doped with a first (n-type) dopant type, so as to have a first conductivity type; and a second region (216) adjacent to the drift region and proximal to a surface (204) of the drift layer. The second region is doped with a second (p-type) dopant type, so as to have a second conductivity type. The semiconductor device further includes a junction termination extension (JTE) (220) disposed adjacent to the second (well) region. The JTE has a width Wjte and comprises a number of discrete regions (221) separated in a first direction and in a second direction and doped with varying concentrations of the second (p-type) dopant type, so as to have an effective doping profile of the second conductivity type of a functional form that generally decreases along a direction away from the edge of the primary blocking junction (230). The width wjte is less than or equal to a multiple of five times the width of the one- dimensional depletion width (Wdepi ID), and the charge tolerance of the semiconductor device is greater than 1.0 xl013 per cm2.
Abstract:
A semiconductor device (200) is provided and includes a substrate (202) comprising silicon carbide; a drift layer (214) disposed over the substrate and comprising a drift region (214) doped with a first (n-type) dopant type, so as to have a first conductivity type; and a second region (216) adjacent to the drift region and proximal to a surface (204) of the drift layer. The second region is doped with a second (p-type) dopant type, so as to have a second conductivity type. The semiconductor device further includes a junction termination extension (JTE) (220) disposed adjacent to the second (well) region. The JTE has a width Wjte and comprises a number of discrete regions (221) separated in a first direction and in a second direction and doped with varying concentrations of the second (p-type) dopant type, so as to have an effective doping profile of the second conductivity type of a functional form that generally decreases along a direction away from the edge of the primary blocking junction (230). The width wjte is less than or equal to a multiple of five times the width of the one- dimensional depletion width (Wdepi ID), and the charge tolerance of the semiconductor device is greater than 1.0 xl013 per cm2.
Abstract:
A silicon carbide device is presented that includes a gate electrode disposed over a portion of a silicon carbide substrate as well as a dielectric film disposed over the gate electrode. The device has a contact region disposed near the gate electrode and has a layer disposed over the dielectric film and over the contact region. The layer includes nickel in portions disposed over the dielectric film and includes nickel silicide in portions disposed over the contact region. The nickel silicide layer is configured to provide an ohmic contact to the contact region of the silicon carbide device.