公开(公告)号：US20140360767A1

公开(公告)日：2014-12-11

申请号：US14294588

申请日：2014-06-03

Applicant: IBIDEN CO., LTD.

Inventor： Makoto TERUI ,  Masatoshi KUNIEDA ,  Yoshinori SHIZUNO ,  Asuka Il

IPC: H05K1/11 ,  H05K3/12

CPC classification number: H01L24/19 ,  H01L23/49816 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12042 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/09136 ,  H05K2201/10159 ,  H01L2924/00

Abstract: A wiring board includes a first insulation layer, first conductive patterns formed on the first insulation layer and including first mounting pads positioned to mount a semiconductor element, a wiring structure positioned in the first insulation layer and including a second insulation layer, second conductive patterns formed on the second insulation layer, and second mounting pads connected to the second conductive patterns, and third mounting pads formed on the first insulation layer above the second mounting pads and connected to the second mounting pads such that the third mounting pads are positioned to mount the semiconductor element and are set off from the second mounting pads toward the semiconductor element.

Abstract translation: 布线板包括第一绝缘层，形成在第一绝缘层上的第一导电图案，并且包括定位成安装半导体元件的第一安装焊盘，位于第一绝缘层中并包括第二绝缘层的布线结构，形成第二导电图案 在第二绝缘层上，以及连接到第二导电图案的第二安装焊盘以及形成在第二安装焊盘上方的第一绝缘层上并连接到第二安装焊盘的第三安装焊盘，使得第三安装焊盘被定位成安装 半导体元件并且从第二安装焊盘朝向半导体元件脱离。

公开(公告)号：US20150060124A1

公开(公告)日：2015-03-05

申请号：US14473235

申请日：2014-08-29

Applicant: IBIDEN CO., LTD.

Inventor： Makoto TERUI ,  Takashi KARIYA ,  Yoshinori SHIZUNO ,  Masatoshi KUNIEDA

IPC: H05K1/11 ,  H05K3/20 ,  H05K3/40 ,  H05K1/02

CPC classification number: H05K1/111 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2924/15313 ,  H05K1/141 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/041 ,  H05K2201/094 ,  H05K2201/09472 ,  H05K2201/09827 ,  H05K2201/10159 ,  H05K2201/10674 ,  H05K2203/0465 ,  Y02P70/611 ,  Y10T29/49128

Abstract: A combined printed wiring board includes a multilayer printed wiring board having an outermost insulation layer, and a wiring film fixed to a portion of the outermost insulation layer of the multilayer printed wiring board. The wiring film includes dense-pitch pads formed on a semiconductor-mounting surface of the wiring film, the multilayer printed wiring board has sparse-pitch pads formed on a semiconductor-mounting surface of the multilayer printed wiring board, the dense-pitch pads are formed to facilitate electrical connection between a first semiconductor element and a second semiconductor element, and the sparse-pitch pads are formed to facilitate electrical connection between the multilayer printed wiring board and the first semiconductor element and/or the second semiconductor element.

Abstract translation: 组合印刷线路板包括具有最外绝缘层的多层印刷布线板和固定到多层印刷线路板的最外层绝缘层的一部分的布线膜。 布线膜包括形成在布线膜的半导体安装表面上的密集垫片，多层印刷布线板具有形成在多层印刷布线板的半导体安装表面上的稀疏间距衬垫，密集衬垫是 形成为促进第一半导体元件和第二半导体元件之间的电连接，并且形成稀疏间距焊盘以便于多层印刷线路板与第一半导体元件和/或第二半导体元件之间的电连接。

公开(公告)号：US20160073515A1

公开(公告)日：2016-03-10

申请号：US14847396

申请日：2015-09-08

Applicant: IBIDEN CO., LTD.

Inventor： Keisuke SHIMIZU ,  Makoto TERUI ,  Ryojiro TOMINAGA ,  Tsutomu YAMAUCHI

IPC: H05K3/32 ,  H05K3/46 ,  H05K3/40 ,  H05K3/00 ,  H05K1/18 ,  H05K1/11

CPC classification number: H05K1/185 ,  H05K1/115 ,  H05K3/421 ,  H05K3/4652 ,  H05K3/4697 ,  H05K2201/09827

Abstract: A wiring board with a built-in electronic component includes a substrate having a cavity, an electronic component accommodated in the cavity and having electrode terminals, an insulating layer formed on the substrate such that the insulating layer is covering the electronic component in the cavity, and via conductors formed through the insulating layer and including first via conductors and second via conductors such that the second via conductors are connected to the electrode terminals of the electronic component, respectively. The via conductors are formed in via formation holes penetrating through the insulating layer, respectively, and the via formation holes include first via formation holes and second via formation holes such that the second via formation holes are exposing the electrode terminals of the electronic component, respectively, and that a second via formation hole has a diameter which is smaller than a diameter of a first via formation hole.

Abstract translation: 具有内置电子部件的布线基板包括具有空腔的基板，容纳在所述空腔中的电子部件，具有电极端子，形成在所述基板上的绝缘层，使得所述绝缘层覆盖所述空腔内的电子部件， 以及通过绝缘层形成的通孔导体，并且包括第一通孔导体和第二通路导体，使得第二通孔导体分别连接到电子部件的电极端子。 通孔导体分别形成在穿过绝缘层的通孔形成孔中，并且通孔形成孔分别包括第一通孔形成孔和第二通孔形成孔，使得第二通孔形成孔分别暴露电子部件的电极端子 并且第二通孔形成孔的直径小于第一通孔形成孔的直径。

公开(公告)号：US20140231990A1

公开(公告)日：2014-08-21

申请号：US14265887

申请日：2014-04-30

Applicant: IBIDEN CO., LTD.

Inventor： Shinji OUCHI ,  Shigeru YAMADA ,  Makoto TERUI ,  Yoshinori SHIZUNO

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49811 ,  H01L21/76885 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02377 ,  H01L2224/0346 ,  H01L2224/03831 ,  H01L2224/0401 ,  H01L2224/0501 ,  H01L2224/05016 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/131 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/351 ,  Y10T29/49165 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor chip and a wiring board formed on the semiconductor chip. The wiring board includes a first insulation layer, first conductive patterns on the first layer, first via conductors formed in the first layer and connecting the first patterns and electrode pads of the chip, respectively, a second insulation layer on the first layer, second conductive patterns on the second layer, and second via conductors formed in the second layer and connecting the first conductive patterns and the second patterns, respectively, each second via conductors has a side surface extending through the second layer such that the side surface has a bent portion which changes inclination of the side surface in depth direction of each second via conductor, and the second patterns are positioned to fan in or out with respect to the electrode pads.

Abstract translation: 半导体器件包括形成在半导体芯片上的半导体芯片和布线板。 布线基板包括第一绝缘层，第一层上的第一导电图案，形成在第一层中的第一通孔导体，分别连接芯片的第一图案和电极焊盘，第一绝缘层，第二导电层 第二层上的图案和形成在第二层中并分别连接第一导电图案和第二图案的第二通孔导体分别具有每个第二通孔导体，具有延伸穿过第二层的侧表面，使得侧表面具有弯曲部分 其改变每个第二通孔导体在深度方向上的侧表面的倾斜度，并且第二图案被定位成相对于电极焊盘进入或者退出。

公开(公告)号：US20160044789A1

公开(公告)日：2016-02-11

申请号：US14819579

申请日：2015-08-06

Applicant: IBIDEN CO., LTD.

Inventor： Keisuke SHIMIZU ,  Makoto TERUI ,  Ryojiro TOMINAGA ,  Yuichi NAKAMURA

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/22 ,  H05K3/28 ,  H05K3/40 ,  H05K3/06 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K1/185 ,  H05K1/0224 ,  H05K3/305 ,  H05K3/429 ,  H05K3/4694 ,  H05K2201/09536 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/2072

Abstract: A wiring board with a cavity for a built-in electronic component includes a conductor layer including a conductor circuit layer and a plane layer, and an insulating layer laminated on the conductor layer and having a cavity such that the cavity is forming an exposed portion of the plane layer and formed to mount a built-in electronic component on the exposed portion of the plane layer. The plane layer has a recess structure formed in an outer peripheral portion in the exposed portion of the plane layer.

Abstract translation: 具有用于内置电子部件的空腔的布线板包括导体层，该导体层包括导体电路层和平面层，以及绝缘层，层压在导体层上并具有空腔，使得空腔形成暴露部分 该平面层并形成为将内置的电子部件安装在平面层的暴露部分上。 平面层具有形成在平面层的露出部分的外周部分中的凹陷结构。

公开(公告)号：US20160020164A1

公开(公告)日：2016-01-21

申请号：US14799846

申请日：2015-07-15

Applicant: IBIDEN CO., LTD.

Inventor： Makoto TERUI ,  Ryojiro Tominaga ,  Masatoshi Kunieda ,  Noriki Sawada

IPC: H01L23/498 ,  C23C18/18 ,  C23C18/16 ,  C23C18/42 ,  C23C18/31 ,  H01L21/48 ,  C23C18/32

CPC classification number: H01L23/49822 ,  C23C18/1651 ,  C23C18/1653 ,  C23C18/31 ,  C23C18/32 ,  C23C18/42 ,  C25D7/00 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/145 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5389 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15313 ,  H05K1/186 ,  H05K3/4007 ,  H05K3/4644 ,  H05K3/4694 ,  H05K3/4697 ,  H05K2201/10378

Abstract: A wiring substrate includes a first outermost conductor layer, a first outermost insulating layer covering the first conductor layer, a second outermost conductor layer formed on opposite side of the first conductor layer, and a second outermost insulating layer covering the second conductor layer. The first insulating layer has first openings such that the first openings are exposing first conductor pads including portions of the first conductor layer, the second insulating layer has second openings such that the second openings are exposing second conductor pads including portions of the second conductor layer, each of the first conductor pads has a first plating layer recessed with respect to outer surface of the first insulating layer, and each of the second conductor pads has a second plating layer formed flush with outer surface of the second insulating layer or having bump shape protruding from the outer surface of the second insulating layer.

Abstract translation: 布线基板包括第一最外导体层，覆盖第一导体层的第一最外绝缘层，形成在第一导体层相对侧的第二最外导体层和覆盖第二导体层的第二最外绝缘层。 第一绝缘层具有第一开口，使得第一开口暴露包括第一导体层的部分的第一导体焊盘，第二绝缘层具有第二开口，使得第二开口暴露包括第二导体层的部分的第二导体焊盘， 每个第一导体焊盘具有相对于第一绝缘层的外表面凹陷的第一镀层，并且每个第二导体焊盘具有与第二绝缘层的外表面齐平或具有突出形状的凸起形状的第二镀层 从第二绝缘层的外表面。

公开(公告)号：US20140311780A1

公开(公告)日：2014-10-23

申请号：US14259522

申请日：2014-04-23

Applicant: IBIDEN CO., LTD.

Inventor： Yoshinori SHIZUNO ,  Makoto TERUI ,  Masatoshi KUNIEDA ,  Asuka Il

IPC: H05K1/02 ,  H05K3/00

CPC classification number: H05K1/0269 ,  H05K3/4644 ,  H05K2201/09918 ,  H05K2203/166

Abstract: An electronic component includes an insulation layer, an alignment mark positioned on a first surface of the insulation layer, and an adhesive layer including an optically opaque agent and formed on the first surface of the insulation layer or a second surface of the insulation layer on the opposite side with respect to the first surface of the insulation layer. The adhesive layer has an opening portion formed at the position corresponding to the alignment mark such that the opening portion exposes the alignment mark directly or through the insulation layer.

Abstract translation: 电子部件包括绝缘层，定位在绝缘层的第一表面上的对准标记，以及包含光不透明剂的粘合剂层，形成在绝缘层的第一表面或绝缘层的第二表面上 相对于绝缘层的第一表面的相对侧。 粘合剂层具有形成在与对准标记对应的位置处的开口部分，使得开口部分直接或通过绝缘层露出对准标记。

公开(公告)号：US20150264817A1

公开(公告)日：2015-09-17

申请号：US14723520

申请日：2015-05-28

Applicant: IBIDEN CO., LTD.

Inventor： Makoto TERUI ,  Daiki KOMATSU ,  Masatoshi KUNIEDA ,  Takashi KARIYA

IPC: H05K3/30 ,  H01L23/00 ,  H05K3/32 ,  H05K3/20 ,  H05K3/10 ,  H05K3/46 ,  H01L25/00 ,  H01L23/498

CPC classification number: H05K3/305 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5382 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2924/12042 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/115 ,  H05K3/10 ,  H05K3/103 ,  H05K3/20 ,  H05K3/32 ,  H05K3/4602 ,  H05K3/4658 ,  H05K3/4694 ,  H05K2201/10159 ,  H05K2201/10378 ,  H05K2201/1053 ,  Y10T29/49128 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2924/014

Abstract: A method for manufacturing a wiring board includes positioning on a first insulation layer a wiring structure including an insulation layer and conductive patterns formed on the insulation layer, forming a second insulation layer on the first insulation layer and the wiring structure such that the wiring structure is interposed between the first insulation layer and the second insulation layer, forming a via conductor through the second insulation layer, and forming conductive patterns on the second insulation layer such that one of the conductive patterns on the second insulation layer is connected to the via conductor in the second insulation layer.

Abstract translation: 一种布线基板的制造方法，其特征在于，在第一绝缘层上具有绝缘层和形成于绝缘层上的导电图案的布线结构，在第一绝缘层和布线结构上形成第二绝缘层，使布线结构为 插入在第一绝缘层和第二绝缘层之间，通过第二绝缘层形成通孔导体，并且在第二绝缘层上形成导电图案，使得第二绝缘层上的导电图案之一连接到通孔导体 第二绝缘层。

公开(公告)号：US20130256000A1

公开(公告)日：2013-10-03

申请号：US13853338

申请日：2013-03-29

Applicant: IBIDEN CO., LTD.

Inventor： Makoto TERUI ,  Daiki Komatsu ,  Masatoshi Kunieda

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15192 ,  H05K3/3436 ,  H05K3/4644 ,  H05K3/4694 ,  H05K2201/10159 ,  H01L2924/00

Abstract: A wiring board includes a first insulation layer, first conductive patterns formed on the first insulation layer, a second insulation layer formed on the first insulation layer and the first conductive patterns and having an opening portion, a wiring structure accommodated in the opening portion of the second insulation layer and including an insulation layer and conductive patterns on the insulation layer, second conductive patterns formed on the second insulation layer; and a via conductor formed in the second insulation layer and connecting one of the first conductive patterns and one of the second conductive patterns.

Abstract translation: 布线板包括第一绝缘层，形成在第一绝缘层上的第一导电图案，形成在第一绝缘层上的第二绝缘层和第一导电图案，并具有开口部分，布置结构容纳在第一绝缘层的开口部分中 第二绝缘层，并且在绝缘层上包括绝缘层和导电图案，形成在第二绝缘层上的第二导电图案; 以及形成在所述第二绝缘层中并连接所述第一导电图案中的一个和所述第二导电图案中的一个的通孔导体。