公开(公告)号：US20220346240A1

公开(公告)日：2022-10-27

申请号：US17723638

申请日：2022-04-19

Applicant: IBIDEN CO., LTD.

Inventor： Keisuke SHIMIZU ,  Kohei SUZUKI

IPC: H05K3/46 ,  H05K3/00 ,  H05K3/28 ,  H05K3/40 ,  C25D5/02 ,  C25D7/00 ,  C23C28/00 ,  C23C18/16

Abstract: A method for manufacturing a wiring substrate includes forming a conductor layer including first and second pads, forming a resin insulating layer on the conductor layer, forming, in the insulating layer, a first opening exposing the first pad and a second opening exposing the second pad, forming a covering layer on the insulating layer such that the covering layer covers the first and second openings, forming a third opening in the covering layer such that the third opening communicates with the first opening and the first pad is exposed in the third opening, forming, on a surface of the first pad, a protective film formed of material different from material forming the conductor layer, removing the covering layer from the insulating layer, and forming a conductor post on the second pad such that the conductor post is formed of material that is same as the material forming the conductor layer.

公开(公告)号：US20170256470A1

公开(公告)日：2017-09-07

申请号：US15451473

申请日：2017-03-07

Applicant: IBIDEN CO., LTD.

Inventor： Hajime SAKAMOTO ,  Keisuke SHIMIZU

IPC: H01L23/16 ,  H01L21/54 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L23/16 ,  H01L21/4857 ,  H01L21/54 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/145 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/1432 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/18162

Abstract: A wiring substrate includes insulating layers including a first insulating layer such that the first insulating layer is positioned at one end of the insulating layers in lamination direction and has an accommodating portion through the first insulating layer, conductive layers laminated on the insulating layers and including a first conductive layer formed on one end side of the first insulating layer in the lamination direction and a second conductive layer formed on the opposite side, and a semiconductor element accommodated in the accommodating portion of the first insulating layer. The insulating layers include the first insulating layer including reinforcing material and a second insulating layer laminated on the first insulating layer such that the second insulating layer is covering the second conductive layer and the semiconductor element and filling gap formed between the first insulating layer and semiconductor element in the accommodating portion and does not contain reinforcing material.

公开(公告)号：US20150034374A1

公开(公告)日：2015-02-05

申请号：US14446475

申请日：2014-07-30

Applicant: IBIDEN CO., LTD.

Inventor： Keisuke SHIMIZU ,  Yuichi NAKAMURA ,  Tsuyoshi YAMAGUCHI

IPC: H05K1/18 ,  H05K3/40 ,  H05K3/30 ,  H01L23/00 ,  H05K1/09

CPC classification number: H01L24/83 ,  H01L2224/04105 ,  H01L2224/16235 ,  H01L2224/19 ,  H01L2224/27464 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/92244 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/187 ,  H05K3/0097 ,  H05K3/4682 ,  H05K2201/068 ,  H05K2203/0156 ,  H05K2203/1536 ,  Y10T29/302 ,  H01L2924/00 ,  H01L2224/83005

Abstract: A printed wiring board includes a first insulation layer, an electronic component built into the first insulation layer, a second insulation layer having a via conductor and formed on a first surface of the first insulation layer, and a conductive film formed on the first insulation layer on the opposite side with respect to the first surface of the first insulation layer such that the conductive film is positioned to face a back surface of the electronic component. The first insulation layer has a coefficient of thermal expansion which is set higher than a coefficient of thermal expansion of the second insulation layer.

Abstract translation: 印刷布线板包括第一绝缘层，内置在第一绝缘层中的电子部件，具有通孔导体并形成在第一绝缘层的第一表面上的第二绝缘层和形成在第一绝缘层上的导电膜 在相对于第一绝缘层的第一表面的相对侧上，使得导电膜定位成面对电子部件的后表面。 第一绝缘层具有设定为高于第二绝缘层的热膨胀系数的热膨胀系数。

公开(公告)号：US20160073515A1

公开(公告)日：2016-03-10

申请号：US14847396

申请日：2015-09-08

Applicant: IBIDEN CO., LTD.

Inventor： Keisuke SHIMIZU ,  Makoto TERUI ,  Ryojiro TOMINAGA ,  Tsutomu YAMAUCHI

IPC: H05K3/32 ,  H05K3/46 ,  H05K3/40 ,  H05K3/00 ,  H05K1/18 ,  H05K1/11

CPC classification number: H05K1/185 ,  H05K1/115 ,  H05K3/421 ,  H05K3/4652 ,  H05K3/4697 ,  H05K2201/09827

Abstract: A wiring board with a built-in electronic component includes a substrate having a cavity, an electronic component accommodated in the cavity and having electrode terminals, an insulating layer formed on the substrate such that the insulating layer is covering the electronic component in the cavity, and via conductors formed through the insulating layer and including first via conductors and second via conductors such that the second via conductors are connected to the electrode terminals of the electronic component, respectively. The via conductors are formed in via formation holes penetrating through the insulating layer, respectively, and the via formation holes include first via formation holes and second via formation holes such that the second via formation holes are exposing the electrode terminals of the electronic component, respectively, and that a second via formation hole has a diameter which is smaller than a diameter of a first via formation hole.

Abstract translation: 具有内置电子部件的布线基板包括具有空腔的基板，容纳在所述空腔中的电子部件，具有电极端子，形成在所述基板上的绝缘层，使得所述绝缘层覆盖所述空腔内的电子部件， 以及通过绝缘层形成的通孔导体，并且包括第一通孔导体和第二通路导体，使得第二通孔导体分别连接到电子部件的电极端子。 通孔导体分别形成在穿过绝缘层的通孔形成孔中，并且通孔形成孔分别包括第一通孔形成孔和第二通孔形成孔，使得第二通孔形成孔分别暴露电子部件的电极端子 并且第二通孔形成孔的直径小于第一通孔形成孔的直径。

公开(公告)号：US20140144686A1

公开(公告)日：2014-05-29

申请号：US14093099

申请日：2013-11-29

Applicant: IBIDEN CO., LTD.

Inventor： Keisuke SHIMIZU

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/30

CPC classification number: H05K1/185 ,  H01L21/568 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/15311 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/09045 ,  H05K2201/09154 ,  H05K2201/09536 ,  H05K2203/167 ,  Y10T29/49139 ,  H01L2924/00

Abstract: A wiring board for a built-in electronic component includes a substrate having a cavity portion, an electronic component accommodated in the cavity portion of the substrate, a filling resin material filling a space formed between the electronic component and an inner wall of the substrate forming the cavity portion, an insulation layer formed on the substrate and the electronic component accommodated in the cavity portion of the substrate, and a via conductor formed in the insulation layer such that the via conductor is connected to a connection terminal of the electronic component. The substrate has projection portions formed on the inner wall of the substrate such that the projection portions project toward the electronic component accommodated in the cavity portion of the substrate.

Abstract translation: 一种用于内置电子元件的布线板，包括：具有空腔部分的基板;容纳在基板的空腔部分中的电子元件;填充树脂材料，填充电子元件与基板形成的内壁之间形成的空间 空腔部分，形成在基板上的绝缘层和容纳在基板的空腔部分中的电子部件以及形成在绝缘层中的通孔导体，使得通孔导体连接到电子部件的连接端子。 基板具有形成在基板的内壁上的突起部分，使得突出部分朝向容纳在基板的空腔部分中的电子部件突出。

公开(公告)号：US20240237221A9

公开(公告)日：2024-07-11

申请号：US18489921

申请日：2023-10-19

Applicant: IBIDEN CO., LTD.

Inventor： Shogo FUKUI ,  Ryo ANDO ,  Keisuke SHIMIZU

IPC: H05K1/18 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H05K3/00

CPC classification number: H05K1/186 ,  H01L21/4857 ,  H01L21/4864 ,  H01L21/56 ,  H01L23/49822 ,  H01L24/19 ,  H01L24/20 ,  H05K3/0035 ,  H05K3/0055 ,  H01L25/0652

Abstract: A method for manufacturing a wiring substrate includes forming conductor pads on a surface of an insulating layer, positioning, on or in the insulating layer, an electronic component having electrode pads, forming a second insulating layer covering the surface of the insulating layer, conductor pads and electronic component, forming first via holes exposing the conductor pads, applying a first desmear treatment to the second insulating layer such that residues are removed from the first via holes, forming second via holes in the second insulating layer after the first desmear treatment such that the second via holes expose the electrode pads of the electronic component positioned on or in the insulating layer, applying a second desmear treatment to the second insulating layer such that residues are removed from the second via holes, forming first via conductors in the first via holes, and forming second via conductors in the second via holes.

公开(公告)号：US20230076560A1

公开(公告)日：2023-03-09

申请号：US17821534

申请日：2022-08-23

Applicant: IBIDEN CO., LTD.

Inventor： Keisuke SHIMIZU ,  Tomoyuki IKEDA

IPC: G02B6/42 ,  H01L25/16

Abstract: A semiconductor package includes a printed wiring board, a logic IC mounted on a first surface of the board, a connector mounted on a second surface of the board on the opposite side with respect to the first surface, an optical element that converts an optical signal and an electrical signal and positioned on the opposite side with respect to the first surface such that the optical element is at least partially embedded in the board, a path that is formed in the board and electrically connects the logic IC on the first surface and the optical element on the opposite side with respect to the first surface, and an optical waveguide that is embedded on the opposite side with respect to the first surface and optically connects the connector on the second surface and the optical element on the opposite side with respect to the first surface.

公开(公告)号：US20160044789A1

公开(公告)日：2016-02-11

申请号：US14819579

申请日：2015-08-06

Applicant: IBIDEN CO., LTD.

Inventor： Keisuke SHIMIZU ,  Makoto TERUI ,  Ryojiro TOMINAGA ,  Yuichi NAKAMURA

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/22 ,  H05K3/28 ,  H05K3/40 ,  H05K3/06 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K1/185 ,  H05K1/0224 ,  H05K3/305 ,  H05K3/429 ,  H05K3/4694 ,  H05K2201/09536 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/2072

Abstract: A wiring board with a cavity for a built-in electronic component includes a conductor layer including a conductor circuit layer and a plane layer, and an insulating layer laminated on the conductor layer and having a cavity such that the cavity is forming an exposed portion of the plane layer and formed to mount a built-in electronic component on the exposed portion of the plane layer. The plane layer has a recess structure formed in an outer peripheral portion in the exposed portion of the plane layer.

Abstract translation: 具有用于内置电子部件的空腔的布线板包括导体层，该导体层包括导体电路层和平面层，以及绝缘层，层压在导体层上并具有空腔，使得空腔形成暴露部分 该平面层并形成为将内置的电子部件安装在平面层的暴露部分上。 平面层具有形成在平面层的露出部分的外周部分中的凹陷结构。

公开(公告)号：US20240237204A1

公开(公告)日：2024-07-11

申请号：US18408629

申请日：2024-01-10

Applicant: IBIDEN CO., LTD.

Inventor： Keisuke SHIMIZU ,  Fumio NISHIWAKI ,  Ryoya KIMURA

IPC: H05K1/02

CPC classification number: H05K1/0298 ,  H05K2201/0209 ,  H05K2201/0242

Abstract: A wiring substrate includes a first wiring part including a first insulating layer and a first conductor layer laminated on the first insulating layer, and a second wiring part including a second insulating layer and a second conductor layer laminated on the second insulating layer. The thickness of the second insulating layer is smaller than that of the first insulating layer. The thickness of the second conductor layer is smaller than that of the first conductor layer. The first conductor layer includes first wirings including differential wirings having the minimum wiring width of larger than 5 μm and minimum inter-wiring distance of larger than 7 μm. The second conductor layer includes second wirings having the maximum wiring width of 5 μm or less and the maximum inter-wiring distance of 7 μm or less. The second part is positioned closer to the outermost surface of the substrate than the first part.

公开(公告)号：US20240234326A9

公开(公告)日：2024-07-11

申请号：US18489952

申请日：2023-10-19

Applicant: IBIDEN CO., LTD.

Inventor： Ikuya TERAUCHI ,  Shogo FUKUI ,  Ryo ANDO ,  Keisuke SHIMIZU

IPC: H01L23/538 ,  H05K1/11

CPC classification number: H01L23/5383 ,  H01L23/5386 ,  H05K1/116 ,  H05K2201/0939 ,  H05K2201/094

Abstract: A wiring substrate includes first conductor pads formed on a surface of an insulating layer, second conductor pads formed on the surface of the insulating layer, a second insulating layer covering the surface of the insulating layer and first and second conductor pads, first via conductors formed in first via holes penetrating through the second insulating layer such that the first via conductors are formed on the first conductor pads, and second via conductors formed in second via holes penetrating through the second insulating layer such that the second via conductors are formed on the second conductor pads. The first and second conductor pads are formed such that an annular width amount of each second conductor pad is smaller than an annular width amount of each first conductor pad and that a haloing amount in each second conductor pad is smaller than a haloing amount in each first conductor pad.