公开(公告)号：US20150216049A1

公开(公告)日：2015-07-30

申请号：US14680371

申请日：2015-04-07

Applicant: IBIDEN CO., LTD.

Inventor： Yoshinori SHIZUNO ,  Nobuya TAKAHASHI ,  Hisayuki NAKAGOME ,  Asuka II

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/46 ,  H05K1/02

CPC classification number: H05K1/111 ,  H01L21/563 ,  H01L21/76802 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L25/18 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K1/032 ,  H05K1/11 ,  H05K1/115 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/465 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/10522 ,  H05K2203/06 ,  H05K2203/1453 ,  Y10T156/10 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/014

Abstract: A wiring board includes a first interlayer insulation layer, a second interlayer insulation layer formed on the first interlayer insulation layer and having an opening portion, first conductive pads formed on the second interlayer insulation layer, a conductive plane layer formed on the first interlayer insulation layer such that the conductive plane layer is exposed by the opening portion of the second interlayer insulation layer, a wiring structure positioned directly on the conductive plane layer such that the wiring structure is accommodated in the opening portion of the second interlayer insulation layer, and second conductive pads formed on the wiring structure such that the first conductive pads and the second conductive pads are set to be positioned on a same plane.

Abstract translation: 布线板包括第一层间绝缘层，形成在第一层间绝缘层上并具有开口部分的第二层间绝缘层，形成在第二层间绝缘层上的第一导电焊盘，形成在第一层间绝缘层上的导电平面层 使得导电平面层由第二层间绝缘层的开口部分露出，直接位于导电平面层上的布线结构使得布线结构容纳在第二层间绝缘层的开口部分中，并且第二导电 形成在布线结构上的焊盘，使得第一导电焊盘和第二导电焊盘被设置在同一平面上。

公开(公告)号：US20150255359A1

公开(公告)日：2015-09-10

申请号：US14719376

申请日：2015-05-22

Applicant: IBIDEN CO., LTD.

Inventor： Toshiki FURUTANI ,  Daiki KOMATSU ,  Nobuya TAKAHASHI

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L21/78 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/3114 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76804 ,  H01L21/78 ,  H01L23/28 ,  H01L23/29 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/562 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/83

Abstract: An electronic component including a wiring board having interlayer insulation layers and conductive patterns, the wiring board having a first surface and a second surface on the opposite side of the first surface, multiple first bumps formed on a first conductive pattern positioned on the first surface of the wiring board among the conductive patterns of the wiring board, a semiconductor element mounted on the first surface of the wiring board through the first bumps, an encapsulating resin encapsulating the semiconductor element and at least a portion of a side surface of the wiring board, the side surface of the wiring board extending between the first surface and second surface of the wiring board, and multiple of second bumps formed on the second surface of the wiring board and connected to a second conductive pattern of the conductive patterns in the wiring board.

Abstract translation: 一种电子部件，包括具有层间绝缘层和导电图案的布线基板，所述布线板具有在所述第一面的相反侧的第一表面和第二表面，形成在位于所述第一表面的第一表面的第一表面上的第一导电图案上的多个第一凸起 布线板的导体图案中的布线板，通过第一凸块安装在布线板的第一表面上的半导体元件，封装半导体元件的封装树脂和布线板的侧面的至少一部分， 所述布线板的所述侧面在所述布线基板的所述第一表面和所述第二表面之间延伸，以及形成在所述布线板的所述第二表面上并连接到所述布线板中的所述导电图案的第二导电图案的多个第二凸块。

公开(公告)号：US20150245485A1

公开(公告)日：2015-08-27

申请号：US14628477

申请日：2015-02-23

Applicant: IBIDEN CO., LTD.

Inventor： Nobuya TAKAHASHI ,  Shigeru YAMADA ,  Takashi KARIYA

IPC: H05K1/11 ,  H05K3/18 ,  H05K3/30

CPC classification number: H05K1/113 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K3/4694 ,  H05K2201/094 ,  H05K2201/09972 ,  H05K2201/10522 ,  H05K2201/10674 ,  Y10T29/49144

Abstract: A printed wiring board includes a first insulating layer, a first conductor layer formed on a surface of the first insulating layer and including first pads, and a wiring structure including a second conductor layer formed on the first insulating layer, a second insulating layer laminated on the second conductor layer, a third conductor layer formed on the second insulating layer, and formed through the second insulating layer. The second conductor layer includes second pads formed on the first insulating layer, the third conductor layer includes third pads formed on the second insulating layer, the via conductors are positioned such that the via conductors are connecting the second pads and the third conductor layer, and the wiring structure is formed such that the second conductor layer and third conductor layer are not electrically connected to the first conductor layer.

Abstract translation: 印刷布线板包括第一绝缘层，形成在第一绝缘层的表面上并包括第一焊盘的第一导体层，以及包括形成在第一绝缘层上的第二导体层的布线结构，层叠在第一绝缘层上的第二绝缘层 第二导体层，形成在第二绝缘层上的第三导体层，并通过第二绝缘层形成。 所述第二导体层包括形成在所述第一绝缘层上的第二焊盘，所述第三导体层包括形成在所述第二绝缘层上的第三焊盘，所述通孔导体定位成使得所述通孔导体连接所述第二焊盘和所述第三导体层，以及 布线结构形成为使得第二导体层和第三导体层不与第一导体层电连接。

公开(公告)号：US20160066423A1

公开(公告)日：2016-03-03

申请号：US14841923

申请日：2015-09-01

Applicant: IBIDEN CO., LTD.

Inventor： Hajime SAKAMOTO ,  Nobuya TAKAHASHI

IPC: H05K1/11 ,  H05K3/10 ,  H05K3/00 ,  H05K1/14

CPC classification number: H01L23/49822 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/02 ,  H05K1/113 ,  H05K1/141 ,  H05K1/181 ,  H05K3/0017 ,  H05K3/108 ,  H05K3/4694 ,  H05K2201/0769 ,  H05K2201/09036 ,  H05K2201/10522 ,  H05K2201/1053 ,  H05K2201/10674 ,  Y02P70/611

Abstract: A printed wiring board includes an insulating layer including insulating material, and a conductor layer formed on a surface of the insulating layer and including conductor pads and conductor patterns such that the conductor pads are positioned to connect one or more electronic components and that the conductor patterns are formed between the conductor pads. The conductor patterns are formed such that each conductor pattern has a pattern width of 3 μm or less and that the conductor patterns have a pattern interval of 3 μm or less between adjacent conductor patterns, and the insulating layer has recess portions formed on the surface between the conductor patterns at least along the conductor patterns such that the recess portions have a depth in a range of 0.1 μm to 2.0 μm relative to a contact interface at which the conductor patterns and the insulating layer are in contact with each other.

Abstract translation: 印刷电路板包括绝缘层，其包括绝缘材料，以及形成在绝缘层的表面上并包括导体焊盘和导体图案的导体层，使得导体焊盘定位成连接一个或多个电子部件，导体图案 形成在导体焊盘之间。 导体图案形成为使得每个导体图案具有3μm或更小的图案宽度，并且导体图案在相邻导体图案之间具有3μm或更小的图案间隔，并且绝缘层具有形成在其间的表面上的凹部 所述导体图案至少沿着所述导体图案，使得所述凹部相对于所述导体图案和所述绝缘层彼此接触的接触界面具有在0.1μm至2.0μm的范围内的深度。

公开(公告)号：US20160037629A1

公开(公告)日：2016-02-04

申请号：US14813218

申请日：2015-07-30

Applicant: IBIDEN CO., LTD.

Inventor： Nobuya TAKAHASHI

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/03 ,  H05K1/09

CPC classification number: H05K3/18 ,  H01L21/4857 ,  H01L23/49866 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/0296 ,  H05K1/0313 ,  H05K1/09 ,  H05K1/111 ,  H05K1/141 ,  H05K3/16 ,  H05K3/4007 ,  H05K2201/0326 ,  H05K2201/0364 ,  H05K2201/0391 ,  H05K2201/0769 ,  H05K2201/09236 ,  H05K2201/0929 ,  H05K2201/094 ,  H05K2201/09654 ,  H05K2201/097 ,  H05K2201/09736 ,  H05K2201/098 ,  H01L2924/014

Abstract: A printed wiring board includes an insulation layer, conductive pads formed on the insulation layer and positioned to connect an electronic component, and a conductive wiring pattern including first and second conductive patterns and formed on the insulation layer such that the conductive wiring pattern is extending between the conductive pads. The first pattern includes first wiring lines, the second pattern includes second wiring lines, the first and second conductive patterns are formed such that the first wiring lines and the second wiring lines are alternately arrayed on the insulation layer, each of the first wiring lines includes a first metal layer formed on an interface with the insulation layer, each of the second wiring lines includes a second metal layer formed on an interface with the insulation layer, and the first metal layer includes a metal material which is different from a metal material forming the second metal layer.

Abstract translation: 印刷布线板包括绝缘层，形成在绝缘层上并定位成连接电子部件的导电焊盘和包括第一和第二导电图案并形成在绝缘层上的导电布线图案，使得导电布线图案在 导电垫。 第一图案包括第一布线，第二图案包括第二布线，第一和第二导电图案形成为使得第一布线和第二布线交替排列在绝缘层上，每个第一布线包括 形成在与所述绝缘层的界面上的第一金属层，每个所述第二布线包括形成在与所述绝缘层的界面上的第二金属层，并且所述第一金属层包括与形成金属的金属材料不同的金属材料 第二金属层。

公开(公告)号：US20140284820A1

公开(公告)日：2014-09-25

申请号：US14295528

申请日：2014-06-04

Applicant: IBIDEN CO., LTD.

Inventor： Toshiki FURUTANI ,  Daiki KOMATSU ,  Masatoshi KUNIEDA ,  Naomi FUJITA ,  Nobuya TAKAHASHI

IPC: H05K1/11 ,  H05K1/02 ,  H01L23/28

CPC classification number: H05K1/113 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/147 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/562 ,  H01L24/82 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2924/00013 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H05K1/0298 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A substrate for mounting a semiconductor includes a first insulation layer having first and second surfaces on the opposite sides and having a penetrating hole penetrating through the first insulation layer, an electrode formed in the penetrating hole in the first insulation layer and having a protruding portion protruding from the second surface of the first insulation layer, a first conductive pattern formed on the first surface of the first insulation layer and connected to the electrode, a second insulation layer formed on the first surface of the first insulation layer and the first conductive pattern and having a penetrating hole penetrating through the second insulating layer, a second conductive pattern formed on the second insulation layer and for mounting a semiconductor element, and a via conductor formed in the penetrating hole in the second insulation layer and connecting the first and second conductive patterns.