公开(公告)号：MY134208A

公开(公告)日：2007-11-30

申请号：MYPI20021771

申请日：2002-05-16

Applicant: IBM

Inventor： GREGORY G FREEMAN ,  DAVID C AHLGREN ,  FENG YI HUANG ,  ADAM D TICKNOR

IPC: H01L29/76 ,  H01L21/00 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/737

Abstract: A PROCESS FOR FORMING A BIPOLAR TRANSISTOR WITH A RAISED EXTRINSIC BASE, AN EMITTER, AND A COLLECTOR INTEGRATER WITH A CMOS CIRCUIT WITH A GATE. AN INTERMEDIATE SEMICONDUCTOR STRUCTURE IS PROVIDED HAVING CMOS AND BIPOLAR AREAS. AN INTRINSIC BASE LAYER IS PROVIDED IN THE BIPOLAR AREA. A BASE OXIDE IS FORMED ACROSS, AND A SACRIFICIAL EMITTER STACK SILICON LAYER IS DEPOSITED ON, BOTH THE CMOS AND BIPOLAR AREAS. A PHOTORESISTIS APPLIED TO PROTECT THE BIPOLAR AREA AND THE STRUCTURE IS ETCHED TO REMOVE THE SACRIFICIAL LAYER FROM THE CMOS AREA ONLY SUCH THAT THE TOP SURFACE OF THE SACRIFICIAL LAYER ON THE BIPOLAR STOP LAYER IS DEPOSITED HAVING A SUBSTANTIALLY FLUSH WITH THE TOP SURFACE OF THE CMOS AREA. FINALLY, A POLISH STOP LAYER IS DEPOSITED HAVING A SUBSTANTIALLY FLAT TOP SURFACE ACROSS BOTHTHE CMOS AND BIPOLAR AREAS SUITABLE FOR SUBSEQUENT CHEMICAL-MECHANICAL POLISHING (CMP) TO FORM THE RAISED EXTRINSIC BASE.

公开(公告)号：SG87156A1

公开(公告)日：2002-03-19

申请号：SG200004528

申请日：2000-08-16

Applicant: IBM

Inventor： KARL E BOGGS ,  KENNETH M DAVIS ,  WILLIAM F LANDERS ,  MICHAEL F LOFARO ,  ADAM D TICKNOR ,  RONALD D FIEGE

IPC: B24B37/30 ,  B24B37/32 ,  B24B49/12 ,  B24B49/16 ,  H01L21/302 ,  H01L21/304

Abstract: A chemical-mechanical polishing (CMP) control system controls distribution of pressure across the backside of a semiconductor wafer being polished. The system includes a CMP apparatus having a carrier for supporting a semiconductor wafer. The carrier includes a plurality of dual function piezoelectric actuators. The actuators sense pressure variations across the semiconductor wafer and are individually controllable. A control is connected to the actuators for monitoring sensed pressure variations and controlling the actuators to provide a controlled pressure distribution across the semiconductor wafer.