公开(公告)号：GB2529425A

公开(公告)日：2016-02-24

申请号：GB201414711

申请日：2014-08-19

Applicant: IBM

Inventor： HAGSPIEL NORBERT ,  KLEIN MATTHIAS ,  JUNGHANS SASCHA ,  WALTER JOERG ,  AMBROLADZE ELATEROMA M

IPC: G06F13/28

Abstract: A data processing apparatus 1 comprises: a number of processor cores 2a, 2b; a shared processor cache 3 connected to each of the processor cores and to a main memory 6; a bus controller 4 connected to the shared processor cache and configured, in response to receiving a descriptor sent S100, S105, S140 by one of the processor cores, to perform a transfer S155 of requested data indicated by the descriptor from the shared processor cache to an I/O device 7; a bus unit 5 connected to the bus controller and configured for transferring data to/from the I/O device; where the shared processor cache comprises means for prefetching the requested data from the shared processor cache or main memory by performing a direct memory access S125 in response to receiving a descriptor from one of the processor cores. The descriptor may comprise address and length information. Efficient data transfer with reduced latency is facilitated.