公开(公告)号：GB2527108A

公开(公告)日：2015-12-16

申请号：GB201410488

申请日：2014-06-12

Applicant: IBM

Inventor： HAGSPIEL NORBERT ,  KLEIN MATTHIAS ,  JUNGHANS SASCHA ,  WALTER JOERG

IPC: G06F1/12 ,  G06F5/06 ,  G06F11/36 ,  G06F13/14 ,  G06F13/38

Abstract: Apparatus (10) for tracing data (24) from a data bus (20) in a first clock domain (12) operating at a first clock frequency (14) to a trace array (22) in a second clock domain (16) operating at a second clock frequency (18), wherein the first clock frequency is lower than the second clock frequency. The apparatus comprises; (i) change detector means (26) to detect a change of the data on the data bus in the first clock domain, (ii) trigger means (28) responsive to the change detector means (26) to send a trigger pulse (34) to the second clock domain, (iii) pulse synchronization means (30) on the second clock domain responsive to the trigger pulse to synchronize the trigger pulse to the second clock frequency of the second clock domain by a meta-stability latch (36), and (iv) data capture means (32) in the second clock domain responsive to the pulse synchronization means to capture data from the data bus and to store the captured data (25) in the trace array.

公开(公告)号：GB2520729A

公开(公告)日：2015-06-03

申请号：GB201321069

申请日：2013-11-29

Applicant: IBM

Inventor： HAGSPIEL NORBERT ,  KLEIN MATTHIAS ,  WALTER JOERG ,  JUNGHANS SASCHA

IPC: G06F13/28 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0868 ,  G06F12/0871

Abstract: In computer system operation overall system performance may strongly suffer from limitations in the rate of data transfer from the processor to I/O devices. In particular, this applies to a data processing apparatus comprising a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring of data to/from an I/O device. The bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit. The data transfer between the processor cache and I/O devices is managed by the bus controller independent of the processor cores. The descriptor may be created by a processor core and transferred to the bus controller after being written to the shared processor cache by the processor core. The bus controller may fetch data from the main memory to the shared processor cache.

公开(公告)号：GB2529425A

公开(公告)日：2016-02-24

申请号：GB201414711

申请日：2014-08-19

Applicant: IBM

Inventor： HAGSPIEL NORBERT ,  KLEIN MATTHIAS ,  JUNGHANS SASCHA ,  WALTER JOERG ,  AMBROLADZE ELATEROMA M

IPC: G06F13/28

Abstract: A data processing apparatus 1 comprises: a number of processor cores 2a, 2b; a shared processor cache 3 connected to each of the processor cores and to a main memory 6; a bus controller 4 connected to the shared processor cache and configured, in response to receiving a descriptor sent S100, S105, S140 by one of the processor cores, to perform a transfer S155 of requested data indicated by the descriptor from the shared processor cache to an I/O device 7; a bus unit 5 connected to the bus controller and configured for transferring data to/from the I/O device; where the shared processor cache comprises means for prefetching the requested data from the shared processor cache or main memory by performing a direct memory access S125 in response to receiving a descriptor from one of the processor cores. The descriptor may comprise address and length information. Efficient data transfer with reduced latency is facilitated.

公开(公告)号：GB2462897A

公开(公告)日：2010-03-03

申请号：GB0909104

申请日：2009-05-28

Applicant: IBM

Inventor： WALTER JOERG ,  FELTEN LOTHAR ,  URBAN VOLKER ,  SMITH CHRISTOPHER

IPC: G06F11/26 ,  G01R31/317

Abstract: A method of debugging a hardware data processing device 10 having at least one state holding element and at least one logic unit with at least one combinatorial logic element, comprises extracting S10 a state of the device preferably by connecting the state holding elements of the device together to form at least one scan chain, the values of which are read out in a chip dump data file. The extracted state is transformed S20 into facilities and/or signal names used by a simulation model. Bits of the chip dump data file may be clustered in values corresponding with elements of the simulation model. The mapped facilities and/or signal names are loaded S30 into a simulator including the simulation model preferably by mapping them into a model initialisation file. The simulation model is run, preferably to evaluate S50 at least one logic unit without updating the state holding elements to generate an all event trace 30 which is just one cycle long and shows a transient value reconstruction. Alternatively, running the simulator model may comprise applying a clock signal and inputting external stimuli to generate an all event trace corresponding with the number of simulation cycles.