公开(公告)号：JP2002261599A

公开(公告)日：2002-09-13

申请号：JP2001368652

申请日：2001-12-03

Applicant: IBM

Inventor： ANAND DARREN L ,  JOHN EDWARD BASS JR ,  FIFIELD JOHN ATKINSON ,  GILLIS PAMELA SUE ,  JAKOBSEN PETER O ,  KEMERER DOUGLAS WAYNE ,  LACKEY DAVID E ,  OAKLAND STEVEN FREDERICK ,  OUELLETTE MICHAEL RICHARD ,  TONTI WILLIAM R

IPC: H01L21/82 ,  G11C7/00 ,  G11C29/00 ,  G11C29/04 ,  H03K19/173

Abstract: PROBLEM TO BE SOLVED: To provide a method and a device for a fuse programming integrated circuit in which fuses are used in common by redundant elements. SOLUTION: A method and a device for initializing an integrated circuit by the use of the compressed data from a remote fuse box are capable of reducing fuses in number required for repairing or customizing the integrated circuit, and grouping the fuses outside macros which are repaired by the fuses. The remote position of the fuses improves the arrangement of the macros, having redundant repairing performances in flexibility and enables the fuses to be properly grouped for facilitating the usability of programming and the layout of circuits. The fuses are formed into columns and rows, to represent control words and run-length compressed data and to provide more repairing points per fuse. The data are loaded into a shift register in series and shifted to macro positions, for controlling the selection of redundant circuits, so that defective integrated circuits can be repaired, and the logic is customized.

公开(公告)号：JP2005071589A

公开(公告)日：2005-03-17

申请号：JP2004243931

申请日：2004-08-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ANAND DARREN L ,  BARTH JR JOHN E

IPC: G11C11/407 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/409

CPC classification number: G11C7/1096 ,  G11C7/1078 ,  G11C11/4076 ,  G11C2207/002 ,  G11C2207/229

Abstract: PROBLEM TO BE SOLVED: To provide a DRAM of a direct writing system and a method that uses a PFET bit switch.
SOLUTION: A control circuit of a memory array device that has one or two related memory cells includes a true bitline connected to one or two memory cells and a complementary bitline. A sense amplifier is connected to the true bitline and the complementary bitline, and the sense amplifier amplifies a small voltage difference between the true bitline and the complementary bitline as a full level signal of a prescribed high and low logic voltage level. The bitline and the sense amplifier are selectively connected to a logic input circuit by the bitline pair, moreover, the bit line pair is constituted so that it connects the true bitline and the complementary bitline before wordline activation related to a cell selected for writing operation. Thereby, before signal formation on the true bitline and the complementary bitline, the writing operation to the selected cell is started.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供直接写入系统的DRAM和使用PFET位开关的方法。 解决方案：具有一个或两个相关存储单元的存储器阵列器件的控制电路包括连接到一个或两个存储器单元的真正位线和互补位线。 读出放大器连接到真位线和互补位线，读出放大器将真位线和互补位线之间的小电压差放大为规定的高和低逻辑电压电平的全电平信号。 位线和读出放大器通过位线对选择性地连接到逻辑输入电路，此外，位线对构成为使得在与被选择用于写入操作的单元相关的字线激活之前连接真位线和互补位线。 因此，在真位线和互补位线上的信号形成之前，开始对所选择的单元的写操作。 版权所有（C）2005，JPO＆NCIPI