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    4.
    发明专利
    未知

    公开(公告)号：DE69120333D1

    公开(公告)日：1996-07-25

    申请号：DE69120333

    申请日：1991-03-01

    Applicant: IBM

    Inventor： FIFIELD JOHN ATKINSON

    IPC: G06F11/10 ,  G06F12/16 ,  G11C11/401 ,  G11C29/00 ,  G11C29/42

    Abstract: An interlocked on-chip ECC system for DRAMs wherein performance degradations due to on-chip ECC are minimized without compromising accurate ECC operations. Several interlocks used in the system insure that the data thereto is valid at certain critical stages. The remainder of the system is allowed to run on a self-timed basis to maximize speed. For example, a dummy data line (DDL) is used to signal the ECC (30) when data from the DRAM arrays (10) is valid during a fetch operation; the same dummy data line (DDL) also signals the DRAM arrays (10) when the data from the ECC (30) is valid during a write-back operation.

    FAULT TOLERANT MEMORY ERROR CORRECTION: EACH MEMORY UNIT HAS LOCK-UP FEATURE
    5.
    发明专利
    FAULT TOLERANT MEMORY ERROR CORRECTION: EACH MEMORY UNIT HAS LOCK-UP FEATURE 未知

    公开(公告)号：NZ232458A

    公开(公告)日：1992-03-26

    申请号：NZ23245890

    申请日：1990-02-09

    Applicant: IBM

    Inventor： BLAKE ROBERT MARTIN ,  BOSSEN DOUGLAS CRAIG ,  CHEN CHIN-LONG ,  FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO ,  LO TIN-CHEE

    IPC: G06F11/10 ,  G06F12/16 ,  G11C29/00 ,  G06F11/00

    Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

    MEMORY ARRAY
    7.
    发明专利
    MEMORY ARRAY 未知

    公开(公告)号：DE3279355D1

    公开(公告)日：1989-02-16

    申请号：DE3279355

    申请日：1982-07-23

    Applicant: IBM

    Inventor： FIFIELD JOHN ATKINSON ,  HELLER LAWRENCE GRIFFITH ,  WALLS LLOYD ANDRE

    IPC: G11C11/404 ,  G11C11/56 ,  G11C27/02 ,  H01L29/78

    Abstract: A dense memory is provided which includes a one device random access memory cell using charge fill and spill techniques wherein a potential well under a storage node is filled with charge and the excess charge above a predetermined level is spilled to a diffusion or drain region connected to a sense line through a channel region controlled by pulses on a word line. One bit or two or more bits of information may be stored in the potential well at any given instant of time. Depending upon the value of the increment of voltage applied to the storage node or electrode, a given analog charge packet is stored in a potential well formed under the storage electrode. Information is read by applying a voltage to the word line to turn on the channel region and then stepping down the voltage on the storage electrode in fractional, preferably one half, increments. Charge from a charge packet spilled from the potential well under the storage electrode is detected by a sensing circuit connected to the sense line. To rewrite information into the potential well, the original increment of voltage is applied to the storage node and the sense line is pulled to ground so that the diffusion region acts as a source of charge for the potential well.

    Fault tolerant memory systems
    8.
    发明专利
    Fault tolerant memory systems 未知

    公开(公告)号：SG44390A1

    公开(公告)日：1997-12-19

    申请号：SG1996000087

    申请日：1990-02-02

    Applicant: IBM

    Inventor： BLAKE ROBERT MARTIN ,  BOSSEN DOUGLAS CRAIG ,  CHEN CHIN-LONG ,  FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO ,  LO TIN-CHEE

    IPC: G06F11/10 ,  G06F12/16 ,  G06F11/00

    Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

    9.
    发明专利
    未知

    公开(公告)号：DE69123372D1

    公开(公告)日：1997-01-16

    申请号：DE69123372

    申请日：1991-01-24

    Applicant: IBM

    Inventor： BARTH JOHN EDWARD ,  DRAKE CHARLES EDWARD ,  FIFIELD JOHN ATKINSON ,  HOVIS WILLIAM PAUL ,  KALTER HOWARD LEO ,  LEWIS SCOTT CLARENCE ,  NICKEL DANIEL JOHN ,  STAPPER CHARLES HENRI ,  YANKOSKY JAMES ANDREW

    IPC: G11C11/401 ,  G06F11/10 ,  G11C29/00 ,  G11C29/42 ,  G06F11/20

    Abstract: A DRAM having on-chip ECC (30) and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section (20), and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry (30) is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block (30) provides both the corrected data bits and the check bits to an SRAM (40). Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM (40) improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

    10.
    发明专利
    未知

    公开(公告)号：DE69026743T2

    公开(公告)日：1996-11-07

    申请号：DE69026743

    申请日：1990-02-02

    Applicant: IBM

    Inventor： BLAKE ROBERT MARTIN ,  BOSSEN DOUGLAS CRAIG ,  CHEN CHIN-LONG ,  FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO ,  LO TIN-CHEE

    IPC: G06F12/16 ,  G06F11/10 ,  G06F11/00

    Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

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