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公开(公告)号:US6444490B2
公开(公告)日:2002-09-03
申请号:US89470601
申请日:2001-06-28
Applicant: IBM
IPC: H01L23/495 , H01L23/498 , H01L25/065 , H05K1/02 , H01L21/44
CPC classification number: H01L23/49816 , H01L23/49524 , H01L23/49531 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L2224/16 , H01L2224/451 , H01L2224/48091 , H01L2224/4824 , H01L2224/73204 , H01L2225/06517 , H01L2225/06527 , H01L2225/06551 , H01L2225/06579 , H01L2924/00013 , H01L2924/01079 , H01L2924/07811 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19107 , H01L2924/30107 , H01L2924/3011 , H05K1/0228 , H01L2924/00014 , H01L2224/29099 , H01L2924/00 , H01L2924/00012
Abstract: Thin-film microflex twisted-wire pair and other connectors are disclosed. Semiconductor packages include microflex technology that electrically connects at least one chip to another level of packaging. Microflex connectors, such as thin-film twisted-wire pair connectors according to the present invention provide superior electrical performance, which includes reduced line inductance, incorporation of integrated passive components, and attachment of discrete passive and active components to the microflex. All of these features enable operation of the chip at increased frequencies.
Abstract translation: 公开了薄膜微纤维双绞线对和其它连接器。 半导体封装包括将至少一个芯片电连接到另一层封装的微技术技术。 根据本发明的诸如薄膜双绞线对连接器的Microflex连接器提供优异的电气性能,其包括降低的线路电感,集成的无源部件的结合以及将离散的被动和有源部件附接到微反射镜。 所有这些特性使芯片在频率增加的情况下能够运行。
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公开(公告)号:JP2002261599A
公开(公告)日:2002-09-13
申请号:JP2001368652
申请日:2001-12-03
Applicant: IBM
Inventor: ANAND DARREN L , JOHN EDWARD BASS JR , FIFIELD JOHN ATKINSON , GILLIS PAMELA SUE , JAKOBSEN PETER O , KEMERER DOUGLAS WAYNE , LACKEY DAVID E , OAKLAND STEVEN FREDERICK , OUELLETTE MICHAEL RICHARD , TONTI WILLIAM R
IPC: H01L21/82 , G11C7/00 , G11C29/00 , G11C29/04 , H03K19/173
Abstract: PROBLEM TO BE SOLVED: To provide a method and a device for a fuse programming integrated circuit in which fuses are used in common by redundant elements. SOLUTION: A method and a device for initializing an integrated circuit by the use of the compressed data from a remote fuse box are capable of reducing fuses in number required for repairing or customizing the integrated circuit, and grouping the fuses outside macros which are repaired by the fuses. The remote position of the fuses improves the arrangement of the macros, having redundant repairing performances in flexibility and enables the fuses to be properly grouped for facilitating the usability of programming and the layout of circuits. The fuses are formed into columns and rows, to represent control words and run-length compressed data and to provide more repairing points per fuse. The data are loaded into a shift register in series and shifted to macro positions, for controlling the selection of redundant circuits, so that defective integrated circuits can be repaired, and the logic is customized.
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3.
公开(公告)号:JP2002319674A
公开(公告)日:2002-10-31
申请号:JP2002035743
申请日:2002-02-13
Applicant: IBM
Inventor: BERTIN CLAUDE LOUIS , DALLY ANTHONY J , FIFIELD JOHN ATKINSON , HIGGINS JOHN JESSE , MANDELMAN JACK ALLAN , TONTI WILLIAM R , HEEL NICHOLAS MARTIN VAN
IPC: H01L21/225 , H01L21/265 , H01L21/28 , H01L21/336 , H01L21/82 , H01L21/8234 , H01L29/423 , H01L29/51 , H01L29/78
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor equipped having a dielectric layer of two-dimensional thickness, and to provide a method of manufacturing the same. SOLUTION: This manufacturing method comprises a first process of forming a mask with a through-hole 20 equipped with a side wall 21 on a structure (a), a second process of implanting suppression chemical seeds 24 into the structure through the through-hole 20 so as to form a suppression region 26 in the structure (b), and a third process of enabling a dielectric layer 28 to grow on the structure in the through-hole 20. Here, the suppression region 26 restrains the dielectric layer 28 partially from growing. By this setup, a self-aligned MOSFET or an anti-fuse device having a low overlap capacitance and a low gate induction drain leakage (i.e., low electric field) can be formed.
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公开(公告)号:DE69120333D1
公开(公告)日:1996-07-25
申请号:DE69120333
申请日:1991-03-01
Applicant: IBM
Inventor: FIFIELD JOHN ATKINSON
IPC: G06F11/10 , G06F12/16 , G11C11/401 , G11C29/00 , G11C29/42
Abstract: An interlocked on-chip ECC system for DRAMs wherein performance degradations due to on-chip ECC are minimized without compromising accurate ECC operations. Several interlocks used in the system insure that the data thereto is valid at certain critical stages. The remainder of the system is allowed to run on a self-timed basis to maximize speed. For example, a dummy data line (DDL) is used to signal the ECC (30) when data from the DRAM arrays (10) is valid during a fetch operation; the same dummy data line (DDL) also signals the DRAM arrays (10) when the data from the ECC (30) is valid during a write-back operation.
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公开(公告)号:NZ232458A
公开(公告)日:1992-03-26
申请号:NZ23245890
申请日:1990-02-09
Applicant: IBM
Inventor: BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO , LO TIN-CHEE
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号:AU615373B2
公开(公告)日:1991-09-26
申请号:AU4939990
申请日:1990-02-09
Applicant: IBM
Inventor: BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号:DE3279355D1
公开(公告)日:1989-02-16
申请号:DE3279355
申请日:1982-07-23
Applicant: IBM
Inventor: FIFIELD JOHN ATKINSON , HELLER LAWRENCE GRIFFITH , WALLS LLOYD ANDRE
IPC: G11C11/404 , G11C11/56 , G11C27/02 , H01L29/78
Abstract: A dense memory is provided which includes a one device random access memory cell using charge fill and spill techniques wherein a potential well under a storage node is filled with charge and the excess charge above a predetermined level is spilled to a diffusion or drain region connected to a sense line through a channel region controlled by pulses on a word line. One bit or two or more bits of information may be stored in the potential well at any given instant of time. Depending upon the value of the increment of voltage applied to the storage node or electrode, a given analog charge packet is stored in a potential well formed under the storage electrode. Information is read by applying a voltage to the word line to turn on the channel region and then stepping down the voltage on the storage electrode in fractional, preferably one half, increments. Charge from a charge packet spilled from the potential well under the storage electrode is detected by a sensing circuit connected to the sense line. To rewrite information into the potential well, the original increment of voltage is applied to the storage node and the sense line is pulled to ground so that the diffusion region acts as a source of charge for the potential well.
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公开(公告)号:SG44390A1
公开(公告)日:1997-12-19
申请号:SG1996000087
申请日:1990-02-02
Applicant: IBM
Inventor: BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO , LO TIN-CHEE
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号:DE69123372D1
公开(公告)日:1997-01-16
申请号:DE69123372
申请日:1991-01-24
Applicant: IBM
Inventor: BARTH JOHN EDWARD , DRAKE CHARLES EDWARD , FIFIELD JOHN ATKINSON , HOVIS WILLIAM PAUL , KALTER HOWARD LEO , LEWIS SCOTT CLARENCE , NICKEL DANIEL JOHN , STAPPER CHARLES HENRI , YANKOSKY JAMES ANDREW
IPC: G11C11/401 , G06F11/10 , G11C29/00 , G11C29/42 , G06F11/20
Abstract: A DRAM having on-chip ECC (30) and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section (20), and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry (30) is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block (30) provides both the corrected data bits and the check bits to an SRAM (40). Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM (40) improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.
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公开(公告)号:DE69026743T2
公开(公告)日:1996-11-07
申请号:DE69026743
申请日:1990-02-02
Applicant: IBM
Inventor: BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO , LO TIN-CHEE
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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