3.
    发明专利
    未知

    公开(公告)号:DE2359150A1

    公开(公告)日:1974-07-11

    申请号:DE2359150

    申请日:1973-11-28

    Applicant: IBM

    Abstract: Disclosed is a true complement generator for providing the true and complement values of an input signal as an output, in response to predetermined timing signals. A first portion of the true complement generator is a gated inverter circuit generating a complement output. A second portion of the true complement generator is a gated driver circuit generating a true output. The true and complement phases of the input signal appear at the respective output nodes during the occurrence of a first timing signal, while both output nodes are held to the same level during the occurrence of a second timing signal.

    4.
    发明专利
    未知

    公开(公告)号:DE2333381A1

    公开(公告)日:1974-01-24

    申请号:DE2333381

    申请日:1973-06-30

    Applicant: IBM

    Abstract: The specification describes a sense amplifier/bit driver circuit having an active bit/sense line pull-up circuit. The active pull-up circuit is shown substantially as two transistors connected between the bit driver circuit and the bit/sense lines. A normal write operation is performed by pulling one bit/sense line to a down level (ground) potential and retaining the other bit/sense line at an up level (positive) voltage. Immediately after the write operation, recovery time is required to bring the down level bit/sense line back to the up level for subsequent read/write operations. The pull-up circuit described in the specification is turned on to perform this function and maintained off in order not to interfere with other operations.

Patent Agency Ranking