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公开(公告)号:JP2002261599A
公开(公告)日:2002-09-13
申请号:JP2001368652
申请日:2001-12-03
Applicant: IBM
Inventor: ANAND DARREN L , JOHN EDWARD BASS JR , FIFIELD JOHN ATKINSON , GILLIS PAMELA SUE , JAKOBSEN PETER O , KEMERER DOUGLAS WAYNE , LACKEY DAVID E , OAKLAND STEVEN FREDERICK , OUELLETTE MICHAEL RICHARD , TONTI WILLIAM R
IPC: H01L21/82 , G11C7/00 , G11C29/00 , G11C29/04 , H03K19/173
Abstract: PROBLEM TO BE SOLVED: To provide a method and a device for a fuse programming integrated circuit in which fuses are used in common by redundant elements. SOLUTION: A method and a device for initializing an integrated circuit by the use of the compressed data from a remote fuse box are capable of reducing fuses in number required for repairing or customizing the integrated circuit, and grouping the fuses outside macros which are repaired by the fuses. The remote position of the fuses improves the arrangement of the macros, having redundant repairing performances in flexibility and enables the fuses to be properly grouped for facilitating the usability of programming and the layout of circuits. The fuses are formed into columns and rows, to represent control words and run-length compressed data and to provide more repairing points per fuse. The data are loaded into a shift register in series and shifted to macro positions, for controlling the selection of redundant circuits, so that defective integrated circuits can be repaired, and the logic is customized.
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公开(公告)号:BR8800754A
公开(公告)日:1988-10-04
申请号:BR8800754
申请日:1988-02-23
Applicant: IBM
Inventor: GOULD ELLIOT LAWRENCE , KEMERER DOUGLAS WAYNE , PIRO RONALD ALAN , RICHARDSON GUY RYMOND , WELLBURN DEBORAH ANN , MCALLISTER LANCE ALAN
IPC: H01L21/82 , H01L21/822 , H01L27/02 , H01L27/04 , H01L27/118 , H01L21/72 , H01L27/10
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公开(公告)号:DE2359150A1
公开(公告)日:1974-07-11
申请号:DE2359150
申请日:1973-11-28
Applicant: IBM
IPC: H03M7/02 , H03K19/096 , H03K19/08
Abstract: Disclosed is a true complement generator for providing the true and complement values of an input signal as an output, in response to predetermined timing signals. A first portion of the true complement generator is a gated inverter circuit generating a complement output. A second portion of the true complement generator is a gated driver circuit generating a true output. The true and complement phases of the input signal appear at the respective output nodes during the occurrence of a first timing signal, while both output nodes are held to the same level during the occurrence of a second timing signal.
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公开(公告)号:DE2333381A1
公开(公告)日:1974-01-24
申请号:DE2333381
申请日:1973-06-30
Applicant: IBM
Inventor: DONOFRIO NICHOLAS MICHAEL , KEMERER DOUGLAS WAYNE
IPC: G11C11/41 , G11C11/414 , G11C11/416 , G11C7/00
Abstract: The specification describes a sense amplifier/bit driver circuit having an active bit/sense line pull-up circuit. The active pull-up circuit is shown substantially as two transistors connected between the bit driver circuit and the bit/sense lines. A normal write operation is performed by pulling one bit/sense line to a down level (ground) potential and retaining the other bit/sense line at an up level (positive) voltage. Immediately after the write operation, recovery time is required to bring the down level bit/sense line back to the up level for subsequent read/write operations. The pull-up circuit described in the specification is turned on to perform this function and maintained off in order not to interfere with other operations.
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