公开(公告)号：US3899777A

公开(公告)日：1975-08-12

申请号：US44603374

申请日：1974-02-25

Applicant: IBM

Inventor： FEICHT ERWIN ,  HAUG WERNER OTTO ,  REMSHARDT ROLF ,  SCHETTLER HELMUT

IPC: G11C11/41 ,  G11C11/414 ,  G11C11/419 ,  H03F3/45 ,  G11C7/06

CPC classification number: G11C11/419 ,  H03F3/45479

Abstract: In a monolithic semiconductor storage the bit lines are selectively connected in pairs to the inputs of a read amplifier. In their separated state the potentials of the read lines (VB) and of the associated input lines of the read amplifier (VBS1, VBS2) show the same value and are derived from a common potential (VH). Potentials VB as well as VBS1 and VBS2 are derived via the same respective number of diode voltage drops from potential VH.

Abstract translation: 在单片半导体存储器中，位线被选择性地与读取放大器的输入成对连接。 在分离状态下，读取放大器（VBS1，VBS2）的读取线（VB）和相关输入线的电位显示相同的值，并从公共电位（VH）导出。 电位VB以及VBS1和VBS2是通过从电位VH相同的相应数量的二极管电压降导出的。

公开(公告)号：US3866176A

公开(公告)日：1975-02-11

申请号：US43815974

申请日：1974-01-31

Applicant: IBM

Inventor： BAITINGER UTZ G ,  HAUG WERNER OTTO ,  ILLI MANFRED

IPC: G11C5/00 ,  G11C8/18 ,  G11C11/34 ,  G11C11/415 ,  G11C11/417 ,  G11C11/418 ,  H03M7/00 ,  H04Q3/00

CPC classification number: G11C11/418 ,  G11C5/00 ,  G11C8/18 ,  G11C11/415 ,  G11C11/417 ,  H03M7/00

Abstract: For each binary position of the coded addresses the selection device shows a phase splitter whose two outputs are connected to associated inputs of decoders. In order to increase the noise resistance jointly clocked AND gates are inserted at the inputs and outputs of the phase splitters, and at the outputs of the decoders. An automatic optimum determination of the conditioning time of the AND gates at the outputs of phase splitters is achieved by a delayed clock pulse DCS1 derived from a clock pulse T of AND gates at the input of the phase splitters. For that purpose, clock pulse T is derived at the output of the AND gates at the input of phase splitters and, via a simulated phase splitter circuit integrated on the chip, is applied as clock pulse DCS1 to the clock inputs of the AND gates at the output of the functional phase splitters. The determination of the conditioning time of AND gates at the output of the decoder is performed accordingly at the output of decoder. In that process, a clock signal is derived from the output of AND gates at the output of phase splitters, and applied as a delayed clock signal DCS2 via a simulation of one of decoders to the clock inputs of the AND gates at the output of the decoders.

Abstract translation: 对于编码地址的每个二进制位置，选择装置示出了一个相位分离器，其两个输出端连接到解码器的相关输入端。 为了提高联合时钟的噪声电阻，并且门分别插入在相位分离器的输入和输出端以及解码器的输出端。