公开(公告)号：WO2012170142A3

公开(公告)日：2013-05-16

申请号：PCT/US2012037212

申请日：2012-05-10

Applicant: IBM ,  YANG CHIH-CHAO ,  COHEN STEPHAN A ,  BAOZHEN LI

Inventor： YANG CHIH-CHAO ,  COHEN STEPHAN A ,  BAOZHEN LI

IPC: H01L29/00 ,  H01L21/205 ,  H01L21/8238

CPC classification number: B82Y10/00 ,  H01L23/5252 ,  H01L29/413 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A switching device (140 or 240) including a first dielectric layer (102 or 207) having a first top surface (108 or 218), two conductive features (104, 106 or 214, 216) embedded in the first dielectric layer (102 or 207), each conductive feature (104, 106 or 214, 216) having a second top surface (110, 112 or 220, 222) that is substantially coplanar with the first top surface (108 or 218) of the first dielectric layer (102 or 207), and a set of discrete islands of a low diffusion mobility metal (114a-c or 204a-c) between the two conductive features (104, 106 or 214, 216). The discrete islands of the low diffusion mobility metal (114a-c or 204a-c) may be either on the first top surface (108) or embedded in the first dielectric layer (207). The electric conductivity across the two conductive features (104, 106 or 214, 216) of the switching device (140 or 240) increases when a prescribed voltage is applied to the two conductive features (104, 106 or 214, 216). A method of forming such a switching device (140 or 240) is also provided.

Abstract translation: 一种包括具有第一顶表面（108或218）的第一介电层（102或207），嵌入第一介电层（102或210）中的两个导电特征（104,106或214,216）的开关装置（140或240） 每个导电特征（104,106或214,216）具有与第一介电层（102）的第一顶表面（108或218）基本上共面的第二顶表面（110,112或220,222） 或207），以及一组在两个导电特征（104,106或214,216）之间的低扩散迁移率金属（114a-c或204a-c）的离散岛。 低扩散迁移率金属（114a-c或204a-c）的离散岛可以在第一顶表面（108）上或嵌入在第一介电层（207）中。 当规定的电压施加到两个导电特征（104,106或214,216）时，开关装置（140或240）的两个导电特征（104,106或214,216）的电导率增加。 还提供了一种形成这种开关装置（140或240）的方法。

公开(公告)号：GB2504879B

公开(公告)日：2014-09-10

申请号：GB201319512

申请日：2012-05-10

Applicant: IBM

Inventor： YANG CHIH-CHAO ,  COHEN STEPHAN A ,  BAOZHEN LI

IPC: H01L23/525

Abstract: A switching device including a first dielectric layer having a first top surface, two conductive features embedded in the first dielectric layer, each conductive feature having a second top surface that is substantially coplanar with the first top surface of the first dielectric layer, and a set of discrete islands of a low diffusion mobility metal between the two conductive features. The discrete islands of the low diffusion mobility metal may be either on the first top surface or embedded in the first dielectric layer. The electric conductivity across the two conductive features of the switching device increases when a prescribed voltage is applied to the two conductive features. A method of forming such a switching device is also provided.

公开(公告)号：GB2504879A

公开(公告)日：2014-02-12

申请号：GB201319512

申请日：2012-05-10

Applicant: IBM

Inventor： YANG CHIH-CHAO ,  COHEN STEPHAN A ,  BAOZHEN LI

IPC: H01L23/525

Abstract: A switching device (140 or 240) including a first dielectric layer (102 or 207) having a first top surface (108 or 218), two conductive features (104, 106 or 214, 216) embedded in the first dielectric layer (102 or 207), each conductive feature (104, 106 or 214, 216) having a second top surface (110, 112 or 220, 222) that is substantially coplanar with the first top surface (108 or 218) of the first dielectric layer (102 or 207), and a set of discrete islands of a low diffusion mobility metal (114a-c or 204a-c) between the two conductive features (104, 106 or 214, 216). The discrete islands of the low diffusion mobility metal (114a-c or 204a-c) may be either on the first top surface (108) or embedded in the first dielectric layer (207). The electric conductivity across the two conductive features (104, 106 or 214, 216) of the switching device (140 or 240) increases when a prescribed voltage is applied to the two conductive features (104, 106 or 214, 216). A method of forming such a switching device (140 or 240) is also provided.

公开(公告)号：GB2601056A

公开(公告)日：2022-05-18

申请号：GB202114896

申请日：2021-10-19

Applicant: IBM

Inventor： JIM SHIH-CHUN LIANG ,  BAOZHEN LI ,  CHIH-CHAO YANG

IPC: H01L23/522

Abstract: The integrated circuit structure includes back end of line (BEOL) wiring layers and capacitor plates (306, 310, 314, 318, 322) formed in an interlayer dielectric device layer. Some of the capacitor electrodes may be formed from the same material as the wiring layers. The capacitor may include multiple interleaved electrode plates that are interconnected by conductive vias 428. The capacitor dielectric layers (316, 320) are formed from high dielectric constant materials such as La2O, ZrO2, and HfO2.