公开(公告)号：JPH11163246A

公开(公告)日：1999-06-18

申请号：JP26252598

申请日：1998-09-17

Applicant: IBM

Inventor： CRONIN JOHN E ,  BARBARA J LUTHER

IPC: H05K3/46 ,  H01L21/306 ,  H01L21/768 ,  H01L23/12 ,  H01L23/522 ,  H01L23/538

Abstract: PROBLEM TO BE SOLVED: To form through vias without additional mask, by forming a second interconnect area in contact with a first insulating layer on a first interconnect area, forming a second insulating layer on an etching stopping layer, and forming an opening which overlaps with an opening in the etching stopping layer. SOLUTION: A nitride etching stopping layer 42, a polyimide insulating layer 44, a nitride etching stopping layer 46, a polyimide insulating layer 48 and nitride etching stopping layer, are deposited in sequence to form a stack. The etching stopping layer 42 is directly deposited on an etching stopping layer 26 in a partial contact with it. This forms a 'hidden mask area'. A resist layer 52 is developed to expose a part of the top of the nitride etching stopping layer 50 and to mark an opening which forms an M3 via interconnect area 54 and multilayer through via multiple connection area 57. In this way, a multilayer through via can be formed through the use of the hidden mask image without additional mask nor interconnect resistor.

公开(公告)号：SG82045A1

公开(公告)日：2001-07-24

申请号：SG1999006335

申请日：1999-12-10

Applicant: IBM

Inventor： PAUL D AGNELLO ,  LEENA P BUCHWALTER ,  JOHN PATRICK HUMMEL ,  BARBARA J LUTHER ,  ANTHONY K STAMPER

IPC: H01L21/04 ,  H01L21/28 ,  H01L23/522 ,  H01L21/318 ,  H01L21/768 ,  H01L21/316 ,  H01L21/325

Abstract: The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure.