Low-resistance low-inductance backside through vias and methods of fabricating the same
    4.
    发明专利
    Low-resistance low-inductance backside through vias and methods of fabricating the same 有权
    通过VIAS的低电阻低电感及其制造方法

    公开(公告)号:JP2013048274A

    公开(公告)日:2013-03-07

    申请号:JP2012233911

    申请日:2012-10-23

    CPC classification number: H01L21/76898 H01L23/481 H01L2924/0002 H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide a backside contact structure and a method of fabricating the structure.SOLUTION: The method includes: forming a first dielectric layer 105 on a frontside of a substrate 100 having the frontside and an opposing backside; forming an electrically conductive first stud contact 140B in the first dielectric layer, the first stud contact extending through the first dielectric layer to the frontside of the substrate; thinning the substrate from the backside of the substrate to form a new backside of the substrate; forming a trench 165 in the substrate, the trench extending from the new backside of the substrate to the first dielectric layer, to expose a bottom surface of the first stud contact in the trench; and forming a conformal electrically conductive layer 170, 175 on the new backside of the substrate, sidewalls of the trench, exposed surfaces of the first dielectric layer and exposed surfaces of the first stud contacts, where the conductive layer is not thick enough to completely fill the trench.

    Abstract translation: 要解决的问题:提供一种背面接触结构和制造该结构的方法。 解决方案:该方法包括:在具有前侧和相对的背面的基板100的前侧形成第一电介质层105; 在所述第一电介质层中形成导电的第一螺柱触头140B,所述第一螺柱触头延伸穿过所述第一电介质层到所述衬底的前侧; 从衬底的背面稀释衬底以形成衬底的新背面; 在衬底中形成沟槽165,沟槽从衬底的新背面延伸到第一介电层,以暴露沟槽中的第一柱形触头的底表面; 并且在衬底的新背面上形成共形导电层170,175,沟槽的侧壁,第一介电层的暴露表面和第一螺柱触头的暴露表面,其中导电层不够厚以至完全填充 沟渠。 版权所有(C)2013,JPO&INPIT

    SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD AS WELL AS FORMING METHOD OF POLYSILICON FUSE AT THE SMALL PITCH IN SEMICONDUCTOR

    公开(公告)号:JPH1084042A

    公开(公告)日:1998-03-31

    申请号:JP21838297

    申请日:1997-08-13

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To lower the pitch of polysilicon.fuse by a method wherein the tungsten at contact level in crack stops is laminated so as to coat the fuse with dielectric at a medium level for fitting a tungsten.barrier to the forming step of the crack stops. SOLUTION: A phosphorus silicate glass 22 is sticked on a substrate 20. Next, the first tungsten films 23 are sticked on the PSG layer 22 at contact level so as to form the tungsten.barrier regions 29 and the crack stops 23. Next, the first metallization layer is formed on the PSG layer 22 to stick an interlayer dielectric layer 24 on the PSG layer. Next, the interlayer dielectric layer 24 is etched away to form the second ring at a barrier level to be filled up with the second tungsten film 30 sticked on the surface of the first tungsten.films 23. Finally, a passivation film 25 and a polyimide layer 26 are sticked on the interlayer dielectric layer 24. Consequently, a thin oxide 21 and the thin interlayer dielectric layer 24 are formed on a polysilicon.fuse 21.

    INCREASING AN ELECTRICAL RESISTANCE OF A RESISTOR BY OXIDATION OR NITRIDIZATION

    公开(公告)号:SG101499A1

    公开(公告)日:2004-01-30

    申请号:SG200106666

    申请日:2001-10-29

    Applicant: IBM

    Abstract: A method for increasing an electrical resistance of a resistor that is within a semiconductor structure. A fraction of a surface layer of the resistor is oxidized with oxygen particles. In an embodiment, the fraction of the surface layer is heated by a beam of particles, such that the semiconductor structure is within a chamber that includes the oxygen particles as gaseous oxygen-comprising molecules. In an embodiment, the semiconductor structure is immersed in a chemical solution which includes the oxygen particles, wherein the oxygen particles includes oxygen-comprising liquid molecules, oxygen ions, or an oxygen-comprising gas dissolved in the chemical solution under pressurization. In an embodiment, the resistor is tested to determine whether the electrical resistance of the resistor after being oxidized with the oxygen particles is within a tolerance of a predetermined target resistance.

    Micro-electro-mechanical system (MEMS) and related actuator bumps, method of manufacture and design structures

    公开(公告)号:GB2505600B

    公开(公告)日:2018-08-01

    申请号:GB201321798

    申请日:2012-03-14

    Applicant: IBM

    Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are provided. The method of forming a MEMS structure includes forming fixed actuator electrodes and a contact point on a substrate. The method further includes forming a MEMS beam over the fixed actuator electrodes and the contact point. The method further includes forming an array of actuator electrodes in alignment with portions of the fixed actuator electrodes, which are sized and dimensioned to prevent the MEMS beam from collapsing on the fixed actuator electrodes after repeating cycling. The array of actuator electrodes are formed in direct contact with at least one of an underside of the MEMS beam and a surface of the fixed actuator electrodes.

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