公开(公告)号：WO02082286A2

公开(公告)日：2002-10-17

申请号：PCT/GB0201484

申请日：2002-03-28

Applicant: IBM ,  IBM UK ,  CIT ALCATEL

Inventor： BARRI PETER ,  CALVIGNAC JEAN ,  HEDDES MARCO ,  LOGAN JOSEPH ,  NIEMEGEERS ALEX ,  VERPLANKEN FABRICE ,  VRANA MIROSLAV

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/18

CPC classification number: G06F13/18 ,  G06F13/161

Abstract: A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.

Abstract translation: 网络处理器（NP）包括允许最大限度利用存储器的控制器。 控制器包括一个内存仲裁器，用于监视NP中请求者的内存访问请求，并授予高优先级请求者每次访问存储器所请求的所有内存带宽。 如果高优先级请求者请求的存储器带宽小于全部存储器带宽，则请求的带宽和全部存储器带宽之间的差异被分配给较低优先权请求者。 通过这样做，每个存储器访问都利用了完整的存储器带宽。

公开(公告)号：AT300763T

公开(公告)日：2005-08-15

申请号：AT02708513

申请日：2002-03-28

Applicant: IBM ,  CIT ALCATEL

Inventor： BARRI PETER ,  CALVIGNAC JEAN ,  HEDDES MARCO ,  LOGAN JOSEPH ,  NIEMEGEERS ALEX ,  VERPLANKEN FABRICE ,  VRANA MIROSLAV

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/18

Abstract: A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.

公开(公告)号：DE60205231D1

公开(公告)日：2005-09-01

申请号：DE60205231

申请日：2002-03-28

Applicant: ALCATEL SA ,  IBM

Inventor： BARRI PETER ,  CALVIGNAC JEAN ,  HEDDES MARCO C O IBM UNITED KI ,  LOGAN JOSEPH ,  NIEMEGEERS ALEX ,  VERPLANKEN FABRICE ,  VRANA MIROSLAV

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/18

Abstract: A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.

公开(公告)号：DE60205231T2

公开(公告)日：2006-05-24

申请号：DE60205231

申请日：2002-03-28

Applicant: ALCATEL SA ,  IBM

Inventor： BARRI PETER ,  CALVIGNAC JEAN ,  HEDDES MARCO ,  LOGAN JOSEPH ,  NIEMEGEERS ALEX ,  VERPLANKEN FABRICE ,  VRANA MIROSLAV

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/18

Abstract: A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.

公开(公告)号：AU2002242874A1

公开(公告)日：2002-10-21

申请号：AU2002242874

申请日：2002-03-28

Applicant: IBM

Inventor： VRANA MIROSLAV ,  CALVIGNAC JEAN ,  VERPLANKEN FABRICE ,  BARRI PETER ,  LOGAN JOSEPH ,  HEDDES MARCO ,  NIEMEGEERS ALEX

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/18

Abstract: A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.