公开(公告)号：WO02082286A2

公开(公告)日：2002-10-17

申请号：PCT/GB0201484

申请日：2002-03-28

Applicant: IBM ,  IBM UK ,  CIT ALCATEL

Inventor： BARRI PETER ,  CALVIGNAC JEAN ,  HEDDES MARCO ,  LOGAN JOSEPH ,  NIEMEGEERS ALEX ,  VERPLANKEN FABRICE ,  VRANA MIROSLAV

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/18

CPC classification number: G06F13/18 ,  G06F13/161

Abstract: A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.

Abstract translation: 网络处理器（NP）包括允许最大限度利用存储器的控制器。 控制器包括一个内存仲裁器，用于监视NP中请求者的内存访问请求，并授予高优先级请求者每次访问存储器所请求的所有内存带宽。 如果高优先级请求者请求的存储器带宽小于全部存储器带宽，则请求的带宽和全部存储器带宽之间的差异被分配给较低优先权请求者。 通过这样做，每个存储器访问都利用了完整的存储器带宽。

公开(公告)号：DE69604294T2

公开(公告)日：2000-04-27

申请号：DE69604294

申请日：1996-05-03

Applicant: IBM ,  IBM DEUTSCHLAND INFORMATIONSSY

Inventor： COHEN ARIEL ,  HOLLAND WILLIAM ,  LOGAN JOSEPH ,  PARASH AVI

IPC: G06F13/36 ,  G06F13/14 ,  G06F15/177 ,  G06F15/16

Abstract: An adapter or add-in card for using in a peripheral component interconnect (PCI) computer includes a universal module which couples the card to the PCI bus. The module includes a set of selectively programmable configuration registers which are loaded by a microprocessor on the adapter. A circuit arrangement on the module issues a command which inhibits the PCI processor from accessing the configuration registers until fully loaded.

公开(公告)号：DE69604294D1

公开(公告)日：1999-10-21

申请号：DE69604294

申请日：1996-05-03

Applicant: IBM ,  IBM DEUTSCHLAND INFORMATIONSSY

Inventor： COHEN ARIEL ,  HOLLAND WILLIAM ,  LOGAN JOSEPH ,  PARASH AVI

IPC: G06F13/36 ,  G06F13/14 ,  G06F15/177 ,  G06F15/16

Abstract: An adapter or add-in card for using in a peripheral component interconnect (PCI) computer includes a universal module which couples the card to the PCI bus. The module includes a set of selectively programmable configuration registers which are loaded by a microprocessor on the adapter. A circuit arrangement on the module issues a command which inhibits the PCI processor from accessing the configuration registers until fully loaded.

公开(公告)号：DE60205231D1

公开(公告)日：2005-09-01

申请号：DE60205231

申请日：2002-03-28

Applicant: ALCATEL SA ,  IBM

Inventor： BARRI PETER ,  CALVIGNAC JEAN ,  HEDDES MARCO C O IBM UNITED KI ,  LOGAN JOSEPH ,  NIEMEGEERS ALEX ,  VERPLANKEN FABRICE ,  VRANA MIROSLAV

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/18

Abstract: A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.

公开(公告)号：DE60205231T2

公开(公告)日：2006-05-24

申请号：DE60205231

申请日：2002-03-28

Applicant: ALCATEL SA ,  IBM

Inventor： BARRI PETER ,  CALVIGNAC JEAN ,  HEDDES MARCO ,  LOGAN JOSEPH ,  NIEMEGEERS ALEX ,  VERPLANKEN FABRICE ,  VRANA MIROSLAV

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/18

Abstract: A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.

公开(公告)号：AU2002242874A1

公开(公告)日：2002-10-21

申请号：AU2002242874

申请日：2002-03-28

Applicant: IBM

Inventor： VRANA MIROSLAV ,  CALVIGNAC JEAN ,  VERPLANKEN FABRICE ,  BARRI PETER ,  LOGAN JOSEPH ,  HEDDES MARCO ,  NIEMEGEERS ALEX

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/18

Abstract: A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.

公开(公告)号：DE69602091D1

公开(公告)日：1999-05-20

申请号：DE69602091

申请日：1996-05-03

Applicant: IBM DEUTSCHLAND INFORMATIONSSY

Inventor： COHEN ARIEL ,  HOLLAND WILLIAM ,  LOGAN JOSEPH ,  PARASH AVI

IPC: G06F13/36 ,  G06F12/06 ,  G06F13/14

Abstract: An adapter or add-in card for use in a peripheral component interconnect (PCI) computer includes a universal module which couples the card to the PCI bus. The module includes a set of selectively programmable configuration registers which are loaded by a microprocessor on the adapter. A circuit arrangement on the module issues a command which inhibits the PCI processor from accessing the configuration registers until fully loaded. Another circuit arrangement presents the Expansion ROM base address register as a 'read/write' register or a read only register with all bits set to logical "0 " to the PCI computer. If the Expansion ROM base address register is presented as a read only register with all bits set to "0 ", the PCI computer concludes that no Expansion ROM exists on the add-in card, and its contents are not shadowed into the memory of the PCI computer. This disabling of the Expansion ROM causes memory space to be conserved in the computer. If the Expansion ROM is presented as a read/write register with non-zero values, the PCI computer concludes that an Expansion ROM exists and "shadows" its contents into the memory of the PCI computer.

公开(公告)号：DE69119241T2

公开(公告)日：1996-11-21

申请号：DE69119241

申请日：1991-08-01

Applicant: IBM

Inventor： LOGAN JOSEPH ,  RUCKEL RAYMOND ,  TOMPKINS ROBERT ,  WESTERFIELD ROBERT

IPC: B23Q3/15 ,  H01L21/683 ,  H02N13/00 ,  H01L21/00

Abstract: An electrostatic chuck 8 assembly includes, from top to bottom: a top multilayer ceramic insulating layer 10; an electrostatic pattern layer 12 having a conductive electrostatic pattern 16 disposed on a multilayer ceramic substrate; a multilayer ceramic support layer 20; and, a heat sink base 30 having a backside cooling channels machined therein. Layers 12, 12 and 20 are bonded together using multilayer ceramic techniques and the heatsink base 30 is brazed to the bottom of the multilayer ceramic support layer 20.

公开(公告)号：DE69119241D1

公开(公告)日：1996-06-05

申请号：DE69119241

申请日：1991-08-01

Applicant: IBM

Inventor： LOGAN JOSEPH ,  RUCKEL RAYMOND ,  TOMPKINS ROBERT ,  WESTERFIELD ROBERT

IPC: B23Q3/15 ,  H01L21/683 ,  H02N13/00 ,  H01L21/00

Abstract: An electrostatic chuck 8 assembly includes, from top to bottom: a top multilayer ceramic insulating layer 10; an electrostatic pattern layer 12 having a conductive electrostatic pattern 16 disposed on a multilayer ceramic substrate; a multilayer ceramic support layer 20; and, a heat sink base 30 having a backside cooling channels machined therein. Layers 12, 12 and 20 are bonded together using multilayer ceramic techniques and the heatsink base 30 is brazed to the bottom of the multilayer ceramic support layer 20.

公开(公告)号：AT300763T

公开(公告)日：2005-08-15

申请号：AT02708513

申请日：2002-03-28

Applicant: IBM ,  CIT ALCATEL

Inventor： BARRI PETER ,  CALVIGNAC JEAN ,  HEDDES MARCO ,  LOGAN JOSEPH ,  NIEMEGEERS ALEX ,  VERPLANKEN FABRICE ,  VRANA MIROSLAV

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/18

Abstract: A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.