公开(公告)号：EP1397830A4

公开(公告)日：2009-03-11

申请号：EP01988335

申请日：2001-12-19

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BOETTCHER STEVEN H ,  HO HERBERT L ,  HOINKIS MARK ,  LEE HYUN KOO ,  WANG YUN-YU ,  WONG KWONG HON

IPC: C23C16/34 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L21/44

CPC classification number: H01L21/76846 ,  H01L21/76858 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer (42) of Ti, followed by a conformal liner layer (46) of CVD TiN, followed in turn by a final liner layer (48) of TA or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the copper to an acceptable amount.

Abstract translation: 在具有铜互连和低k层间电介质的集成电路中，发现热处理后开路的问题，并通过使用Ti的第一衬垫层（42），随后使用CVD共形衬垫层（46） TiN，然后依次是TA或TaN的最终衬垫层（48），因此改善了通孔和下面的铜层之间的粘合性，同时将由Ti和铜之间的合金化引起的电阻的增加减少到可接受的量。

公开(公告)号：WO02056342A3

公开(公告)日：2004-01-08

申请号：PCT/US0149138

申请日：2001-12-19

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BOETTCHER STEVEN H ,  HO HERBERT L ,  HOINKIS MARK ,  LEE HYUN KOO ,  WANG YUN-YU ,  WONG KWONG HON

IPC: C23C16/34 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L21/44 ,  H01L21/4763

CPC classification number: H01L21/76846 ,  H01L21/76858 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer (42) of Ti, followed by a conformal liner layer (46) of CVD TiN, followed in turn by a final liner layer (48) of TA or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the copper to an acceptable amount.

Abstract translation: 在具有铜互连和低k层间电介质的集成电路中，通过使用Ti的第一衬垫层（42），然后使用CVD的保形衬垫层（46），发现并解决了热处理后的开路问题 TiN，然后是TA或TaN的最终衬垫层（48），从而改善通孔和下面的铜层之间的粘附性，同时将由Ti和铜之间的合金化引起的电阻增加减少到可接受的量。

公开(公告)号：AU2002241651A1

公开(公告)日：2002-07-24

申请号：AU2002241651

申请日：2001-12-19

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： WONG KWONG HON ,  LEE HYUN KOO ,  WANG YUN-YU ,  HO HERBERT L ,  HOINKIS MARK ,  BOETTCHER STEVEN H

IPC: C23C16/34 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L21/44 ,  H01L21/4763

Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.

公开(公告)号：DE60141254D1

公开(公告)日：2010-03-25

申请号：DE60141254

申请日：2001-12-19

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： BOETTCHER STEVEN H ,  HO HERBERT L ,  HOINKIS MARK ,  LEE HYUN KOO ,  WANG YUN-YU ,  WONG KWONG HON

IPC: C23C16/34 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.

公开(公告)号：GB2366912A

公开(公告)日：2002-03-20

申请号：GB0106693

申请日：2001-03-16

Applicant: IBM

Inventor： SAMBUCETTI CARLOS J ,  BOETTCHER STEVEN H ,  LOCKE PETER S ,  RUBINO JUDITH M ,  SEO SOON-CHEON

IPC: H01L21/288 ,  H01L21/28 ,  H01L21/3205 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

Abstract: A material lining a via comprises either cobalt XY or nickel XY where X may be tungsten, tin or silicon, and Y is phosphorous or boron, in particular an embodiment disclosing cobalt tungsten phosphide is described. Multilayer linings including TaN are also envisaged. The layers are formed by an electroless plating method. The compounds when used to line a via opening act as a barrier to prevent material (eg copper) from wiring layers diffusing into the surrounding dielectric material.