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    Method for forming porous organic dielectric layer
    4.
    发明专利
    Method for forming porous organic dielectric layer 有权
    用于形成多孔有机电介质层的方法

    公开(公告)号：JP2004336051A

    公开(公告)日：2004-11-25

    申请号：JP2004136335

    申请日：2004-04-30

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： CLEVENGER LAWRENCE A ,  GRECO STEPHEN E ,  KWIETNIAK KEITH T ,  SEO SOON-CHEON ,  YANG CHIH-CHAO ,  WANG YUN-YU ,  WONG KWONG H

    IPC: H01L21/312 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522

    CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76835 ,  H01L21/76856 ,  H01L2221/1036

    Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a wiring layer in an integrated circuit structure.
    SOLUTION: An organic insulating layer is formed, the insulating layer is patterned, a liner is accumulated on the insulating layer, the above structure is exposed in plasma, and a pore is formed in an insulating layer of an area adjacent to the liner. The liner is formed sufficiently thin so that plasma penetrates the liner and the pore is formed on the insulating layer without influencing the liner. During the plasma processing, the plasma penetrates the liner without influencing the liner. After the plasma processing, an additional liner can be accumulated. Thereafter, a conductor is accumulated and an excessive portion of the conductor is deleted from the structure. This method produces an integrated circuit structure including the organic insulating layer having a patterned structure, a liner covering the rear side of the patterned structure, and a conductor filling the patterned structure. The insulating layer includes the pore along the surface area of the insulating layer contacting to the liner, and further, the pore is only existent along the surface area contacting to the liner (where the liner is non-existent inside the pore).
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种用于在集成电路结构中形成布线层的方法。 解决方案：形成有机绝缘层，对绝缘层进行图案化，在绝缘层上积累衬垫，将上述结构暴露在等离子体中，并且在邻近的区域的绝缘层中形成孔 衬垫。 衬垫形成得足够薄，使得等离子体穿透衬垫，并且在绝缘层上形成孔而不影响衬垫。 在等离子体处理期间，等离子体渗透衬垫而不影响衬套。 在等离子体处理之后，可以累积额外的衬垫。 此后，导体被累积，导体的过多部分从结构中删除。 该方法产生包括具有图案化结构的有机绝缘层，覆盖图案化结构的后侧的衬垫和填充图案化结构的导体的集成电路结构。 绝缘层包括沿着与衬垫接触的绝缘层的表面积的孔，此外，孔沿着与衬垫接触的表面区域（其中衬里不存在于孔内）存在。 版权所有（C）2005，JPO＆NCIPI

    PE-ALD OF TaN DIFFUSION BARRIER REGION ON LOW-K MATERIALS
    6.
    发明申请
    PE-ALD OF TaN DIFFUSION BARRIER REGION ON LOW-K MATERIALS 审中-公开
    在低K材料上的TaN扩散障碍区的PE-ALD

    公开(公告)号：WO2005122253A3

    公开(公告)日：2006-12-14

    申请号：PCT/US2005018953

    申请日：2005-05-31

    Applicant: IBM ,  DUNN DERREN N ,  KIM HYUNGJUN ,  ROSSNAGEL STEPHEN M ,  SEO SOON-CHEON

    Inventor： DUNN DERREN N ,  KIM HYUNGJUN ,  ROSSNAGEL STEPHEN M ,  SEO SOON-CHEON

    IPC: H01L21/283 ,  H01L21/285 ,  H01L21/4763 ,  H01L21/52 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

    CPC classification number: H01L21/76846 ,  H01L21/28562 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of depositing a tantalum nitride (TaN) diffusion barrier region on low-k materials. The methods include forming a protective layer (104) on the low-k material substrate (102) by performing plasma-enhanced atomic layer deposition (PE-ALD) from tantalum-based precursor and a nitrogen plasma in a chamber. The protective layer (104) has a nitrogen content greater than its tantalum content. A substantially stoichiometric tantalum-nitride layer is then formed by performing PE-ALD from the tantalum-based precursor and a plasma including hydrogen and nitrogen. The invention also includes the tantalum-nitride diffusion barrier region (108) so formed. In one embodiment, the metal precursor includes tantalum penta-chloride (TaC1 5 ). The invention generates a sharp interface between low-k materials and liner materials.

    Abstract translation: 在低k材料上沉积氮化钽（TaN）扩散阻挡区域的方法。 所述方法包括通过从钽基前体和室中的氮等离子体进行等离子体增强的原子层沉积（PE-ALD）在低k材料衬底（102）上形成保护层（104）。 保护层（104）的氮含量大于钽的含量。 然后通过从钽基前体和包括氢和氮的等离子体中进行PE-ALD形成基本上化学计量的氮化钽层。 本发明还包括如此形成的氮化钽 - 氮化物扩散阻挡区域（108）。 在一个实施方案中，金属前体包括五氯化钽（TaCl 5 N 5）。 本发明在低k材料和衬垫材料之间产生尖锐的界面。

    SUPERFILLED METAL CONTACT VIAS FOR SEMICONDUCTOR DEVICES
    7.
    发明申请
    SUPERFILLED METAL CONTACT VIAS FOR SEMICONDUCTOR DEVICES 审中-公开
    用于半导体器件的超级金属触点VIAS

    公开(公告)号：WO2011084666A3

    公开(公告)日：2011-10-27

    申请号：PCT/US2010060931

    申请日：2010-12-17

    Applicant: IBM ,  KELLY JAMES J ,  BAKER VEERARAGHAVAN S ,  SEO SOON-CHEON ,  HARAN BALA S ,  VO TUAN A

    Inventor： KELLY JAMES J ,  BAKER VEERARAGHAVAN S ,  SEO SOON-CHEON ,  HARAN BALA S ,  VO TUAN A

    IPC: H01L21/28

    CPC classification number: H01L21/2885 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In accordance with one aspect of the invention, a method is provided for fabricating a semiconductor element having a contact via. In such method, a hole (112) can be formed in a dielectric layer (120) to at least partially expose a region (108) including at least one of semiconductor or conductive material. A seed layer (143) can be deposited over a major surface (118) of the dielectric layer and over a surface within the hole (112). In one embodiment, the seed layer (143) can include a metal selected from the group consisting of iridium, osmium, palladium, platinum, rhodium, and ruthenium. A layer (132) consisting essentially of cobalt can be electroplated over the seed layer (143) within the hole (112) to form a contact via (110) in electrically conductive communication with the region.

    Abstract translation: 根据本发明的一个方面，提供了一种用于制造具有接触通孔的半导体元件的方法。 在这种方法中，可以在电介质层（120）中形成孔（112）以至少部分地暴露包括半导体或导电材料中的至少一种的区域（108）。 种子层（143）可以沉积在介电层的主表面（118）之上并且在孔（112）内的表面之上。 在一个实施例中，种子层（143）可以包括选自铱，锇，钯，铂，铑和钌的金属。 可以在孔（112）内的种子层（143）上电镀基本上由钴构成的层（132），以形成与该区域导电连通的接触通孔（110）。

    FinFET with subset of sacrificial fins
    8.
    发明专利
    FinFET with subset of sacrificial fins 未知

    公开(公告)号：GB2497185A

    公开(公告)日：2013-06-05

    申请号：GB201220942

    申请日：2012-11-21

    Applicant: IBM

    Inventor： STANDAERT THEODORUS EDUARDUS ,  HARAN BALASUBRAMANIAN ,  CHENG KANGGUO ,  PONOTH SHOM ,  YAMASHITA TENKO ,  SEO SOON-CHEON

    IPC: H01L29/66

    Abstract: A method of fabricating a FinFET 200 is disclosed which comprises the steps of forming a plurality of fins on a dielectric substrate. A gate layer (208, figure 2A) is deposited over the fins. In some embodiments the fin hardmask that is present on the tops of each fin is removed from some of the fins prior to the deposition of the gate layer. A gate hardmask (210) is then deposited over the gate layer. A portion of the gate hardmask layer and gate layer are then removed. In some embodiments this removal step also removes portions of the fins underneath. In other embodiments portions 202A, 202B, 202C of a subset of fins are removed with an etch. The portion of the etched sacrificial fins that remain are called finlets 220. These finlets remain under the gate of the FinFET. In some embodiments the remaining fins are subsequently merged together.

    10.
    发明专利
    未知

    公开(公告)号：AT470237T

    公开(公告)日：2010-06-15

    申请号：AT03796085

    申请日：2003-12-08

    Applicant: IBM

    Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  LA TULIPE DOUGLAS ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

    IPC: H01L21/768

    Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

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