公开(公告)号：CO4700362A1

公开(公告)日：1998-12-29

申请号：CO92323128

申请日：1990-06-01

Applicant: IBM

Inventor： BONEVENTO FRANCIS M ,  CHISHOLM DOUGLAS R ,  SAMMY D DODDS ,  DHRUVKUMAR M DESAI ,  MANDESE ERNEST N ,  MC NEILL ANDREW B ,  MENDELSON RICHARD N

IPC: G06F13/00 ,  G06F13/12

Abstract: En un sistema procesador de datos que incluye un sistemacentral, y al menos un subsistema que puede llevar dispositivos unidos a él, la combinación que comprende: una interfase de órdenes para transferir información entre el sistema central y dicho un subsistema, incluyendo dicha interfase de órdenes: una primera puerta para recibir una orden directa o una orden indirecta desde dicho sistema central, las cuales órdenes son indicativas del tipo de operación que ha de realizarse en dicho subsistema o en los dispositivos unidos a él; y una segunda puerta para recibir desde dicho sistema central un código indicativo de cual dichas ordenes directa o indirecta se recibe en dicha primera puerta, y siendo también indicativo de cual de dicho un subsistema o de un dispositivo unido a él, ha de ejecutar la orden recibida en dicha primera puerta". En un sistema computador que incluye un procesador central que tiene una memoria del sistema, y al menos un subsistema inteligente que puede tener dispositivos unidos a él, la combinación que comprende: una interfase de órdenes incluida en cada uno de tales subsistemas para transferir información entre dicho procesador central y dicho un subsistema inteligente, incluyendo dicha interfase de órdenes:una puerta de interfase de órdenes para recibir una orden directa o una orden indirecta proveniente de dicho procesador central, las cuales ordenes son indicativas del tipo de operación que ha de realizarse por el subsistema inteligente o los dispositivos unidos a él; yuna puerta de atención, para recibir desde dicho procesador central, un código que tenga una primera porción que es indicativa de cual de dichas órdenes directas o de dichas ordenes indirectas se recibe en dicha puerta de interfase de órdenes; y una segunda porción que es indicativa de cual de los sistemas inteligentes o de los dispositivos unidos a él ha de ejecutar la orden recibida en dicha puerta de interfase de órdenes".

公开(公告)号：BR9002710A

公开(公告)日：1991-08-20

申请号：BR9002710

申请日：1990-06-08

Applicant: IBM

Inventor： BONEVENTO FRANCIS M ,  CHISHOLM DOUGLAS R ,  DODDS SAMMY D ,  DESAI DHRUVKUMAR M ,  MANDESE ERNEST N ,  MCNEILL ANDREW B ,  MENDELSON RICHARD N

IPC: G06F13/12 ,  G06F15/20 ,  G06F13/00

Abstract: A Command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.

公开(公告)号：PH31356A

公开(公告)日：1998-07-31

申请号：PH40473

申请日：1990-05-03

Applicant: IBM

Inventor： BONEVENTO FRANCIS M ,  CHISHOLM DOUGLAS R ,  DOODS SAMMY D ,  DESAI DHRUVKUMAR M ,  MANDESE ERNEST N ,  MCNEILL ANDREW B ,  MENDELSON RICHARD N

IPC: G06F13/12 ,  G06F13/24

Abstract: A Command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.

公开(公告)号：IN177967B

公开(公告)日：1997-03-01

申请号：IN613DE1990

申请日：1990-06-21

Applicant: IBM

Inventor： BONEVENTO FRANCIS M ,  MENDELSON RICHARD N ,  HEATH CHESTER A ,  MANDESE ERNEST N

IPC: G06B29/00

公开(公告)号：CA2025711A1

公开(公告)日：1991-03-23

申请号：CA2025711

申请日：1990-09-19

Applicant: IBM

Inventor： BONEVENTO FRANCIS M ,  MCGOVERN JOSEPH P ,  THOMAS EUGENE M

IPC: G06F15/16 ,  G06F5/06 ,  G06F13/42 ,  G06F13/14

Abstract: A microprocessor system which includes a processor unit with system memory and a separate buffer memory, one or more subsystem adapter units with memory, optional I/O devices which may attach to the adapters, and a bus interface. The memory in the processor and the memory in the adapters are used by the system as a shared memory (106,112) which is configured as a distributed FIFO circular queue (a pipe). Unit to unit asynchronous communication is accomplished by placing control elements (104,116) on the pipe which represent requests, replies, and status information. The units (622,624) send and receive control elements (104,116) independent of the other units which allows free flowing asynchronous delivery of control information and data between units (622,624). The shared memory (106,112) can be organised as pipe pairs between each pair of units to allow full duplex operation by using one pipe for outbound control elements (104,116) and the other pipe for inbound control elements (104,116). The control elements (104,116) have standard fixed header fields with variable fields following the fixed header. The fixed header allows a common interface protocol to be used by different hardware adapters. The combination of the pipe and the common interface protocol allows many different types of hardware adapters to asynchronously communicate, resulting in higher overall throughput due to lower interrupt overhead.

公开(公告)号：CA2012400A1

公开(公告)日：1990-12-09

申请号：CA2012400

申请日：1990-03-16

Applicant: IBM

Inventor： BONEVENTO FRANCIS M ,  CHISHOLM DOUGLAS R ,  DODDS SAMMY D ,  DESAI DHRUVKUMAR M ,  MANDESE ERNEST N ,  MCNEILL ANDREW B ,  MENDELSON RICHARD N

IPC: G06F13/12

Abstract: A Command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.