公开(公告)号：US6433283B2

公开(公告)日：2002-08-13

申请号：US86054901

申请日：2001-05-21

Applicant: IBM

Inventor： BRODSKY WILLIAM L ,  CALETKA DAVID V ,  INFANTOLINO WILLIAM

IPC: H01B7/00 ,  H01B7/08

CPC classification number: H01B7/08 ,  H01B7/0072

Abstract: A ribbon cable includes electrical conductors surrounded by an insulator and vent tubes positioned adjacent and parallel to the conductors and insulator. The vent tubes allow airflow between an internal area of the enclosure and an external atmosphere and prevent access to the internal area of the enclosure.

Abstract translation: 带状电缆包括由绝缘体围绕的电导体和与导体和绝缘体相邻并平行定位的排气管。 通风管允许外壳内部区域和外部气氛之间的气流阻止进入外壳内部区域。

公开(公告)号：JP2004119371A

公开(公告)日：2004-04-15

申请号：JP2003305398

申请日：2003-08-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BRODSKY WILLIAM L ,  BUCHLER JR WILLIAM ,  CHAN BENSON

IPC: H01R33/76 ,  H01L23/32 ,  H01R12/04 ,  H01R13/514 ,  H05K3/32 ,  H05K7/10

CPC classification number: H05K7/1061 ,  H05K3/325 ,  H05K2201/09972 ,  H05K2201/10378 ,  H05K2201/10719

Abstract: PROBLEM TO BE SOLVED: To provide a land grid array (LGA) connector maximizing the quantity of I/O contacts, and to provide its forming method.
SOLUTION: Each LGA section includes at least one set of fingers. Each finger set forms this LGA connector by being connected with a finger set of another section. By forming the LGA connector by this method, the maximum quantity of input/output (I/O) contacts can be provided. Typically, the LGA connector is formed with a plurality (for instance, four) of the individual sections. Each section usually has at least one set (for instance, two sets) of fingers disposed along its outer edge part. Each set of fingers located at a specific section forms the LGA connector by being connected with the finger set of an adjacent different section.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004056126A

公开(公告)日：2004-02-19

申请号：JP2003181880

申请日：2003-06-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ALCOE DAVID J ,  BRODSKY WILLIAM L ,  CALMIDI VARAPRASAD V ,  SATHE SANJEEV B ,  STUTZMAN RANDALL J

IPC: H05K7/20 ,  H01L23/10 ,  H01L23/36 ,  H01L23/40 ,  H01L23/42 ,  H01L23/427 ,  H01L23/34 ,  H01L23/373 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L23/10 ,  H01L23/36 ,  H01L23/42 ,  H01L23/427 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an electronic package which has at least one element and can dissipate heat efficiently.
SOLUTION: This electronic package comprises: a substrate 102 with a first thermal expansion coefficient; a lid 130 with a second thermal expansion coefficient (the first thermal expansion coefficient matches the second thermal expansion coefficient) which is attached to the substrate and has a vapor chamber 160; a thermal transfer medium in contact with the rear surface of each component and the outer surface of the lower wall of the lid; and each component electrically connected to the top surface of the substrate. Thus, efficient cooling can be obtained by means of the vapor chamber while minimizing stress which is induced by thermal expansion coefficient mismatch and applied to the package.
COPYRIGHT: (C)2004,JPO

公开(公告)号：GB2362759B

公开(公告)日：2004-08-25

申请号：GB0028820

申请日：2000-11-27

Applicant: IBM

Inventor： BRODSKY WILLIAM L ,  SATHE SANJEEV B ,  THIEL GEORGE H

IPC: H01L23/04 ,  H01L21/304 ,  H01L23/42 ,  H01L29/06

Abstract: A semiconductor chip package having a non-planar chip therein, to reduce the stress concentrations between the chip and cover plate. In particular, a chip and method of forming a chip having a non-planar or "domed" back surface, wherein the thickness of the non-planar chip is greatest substantially near the center of the chip. Further, a method of rounding the edges or corners of the chip to reduce crack propagation originating at the edges of the chip.

公开(公告)号：GB2362759A

公开(公告)日：2001-11-28

申请号：GB0028820

申请日：2000-11-27

Applicant: IBM

Inventor： BRODSKY WILLIAM L ,  SATHE SANJEEV B ,  THIEL GEORGE H

IPC: H01L23/04 ,  H01L21/304 ,  H01L23/42 ,  H01L29/06

Abstract: An electronic package 50 has an electronic component 58 with a first surface 59 electrically mounted to a substrate 54 and a second arcuate surface 64 with a contour such that the distance between the first surface and the second arcuate surface is greatest substantially near the centre of the electronic component. A method of forming a electronic package comprises providing an electronic component 58 with a first featured surface 59 and a second surface 64, and removing a portion of the second surface 64 so that the second surface 64 is substantially arcuate, with a thickness greatest substantially near the centre of the electronic component. A cap, cover plate, or heat sink 62, maybe mounted on a carrier 52 and the chip 58 by an adhesive 66. In alternative method of forming a chip, an electronic component is provided with a first featured surface and a second planar surface, a first portion of the second planar surface is removed to form a first arcuate surface and the second portion of the second planar surface is removed to form a second arcuate surface. A method of forming an electronic package having at least one profiled edge is also disclosed. A concave profiling tool 120 may be used to grind the shape of the chip.