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公开(公告)号:US6433283B2
公开(公告)日:2002-08-13
申请号:US86054901
申请日:2001-05-21
Applicant: IBM
Inventor: BRODSKY WILLIAM L , CALETKA DAVID V , INFANTOLINO WILLIAM
CPC classification number: H01B7/08 , H01B7/0072
Abstract: A ribbon cable includes electrical conductors surrounded by an insulator and vent tubes positioned adjacent and parallel to the conductors and insulator. The vent tubes allow airflow between an internal area of the enclosure and an external atmosphere and prevent access to the internal area of the enclosure.
Abstract translation: 带状电缆包括由绝缘体围绕的电导体和与导体和绝缘体相邻并平行定位的排气管。 通风管允许外壳内部区域和外部气氛之间的气流阻止进入外壳内部区域。
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公开(公告)号:JP2002043494A
公开(公告)日:2002-02-08
申请号:JP2001194587
申请日:2001-06-27
Applicant: IBM
Inventor: CALETKA DAVID V , CARPER JAMES L , CINCOTTA JOHN P , HORSFORD KIBBY B , IRISH GARY H , LAJZA JOHN J JR , OSBORNE GORDON C JR , RAMSEY CHARLES R , SMITH ROBERT M , VADNAIS MICHAEL J
IPC: H01L23/28 , H01L21/56 , H01L23/16 , H01L23/495 , H01L23/50
Abstract: PROBLEM TO BE SOLVED: To provide a method for reducing and eliminating the strain of a plastic package. SOLUTION: A semiconductor module includes a semiconductor chip, a lead frame having a lead finger, and a down set member being in a mounting medium for reducing the strain and giving a flat package by balancing thermal stress between the lead finger and the mounting medium. The down set member may be the bent part of the lead frame. The down set member may be another body such as a dummy semiconductor chip.
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公开(公告)号:CA2350057A1
公开(公告)日:2001-12-28
申请号:CA2350057
申请日:2001-06-07
Applicant: IBM
Inventor: CALETKA DAVID V , LAJZA JOHN J JR , IRISH GARY H , CARPER JAMES L , RAMSEY CHARLES R , VADNAIS MICHAEL J , CINCOTTA JOHN P , HORSFORD KIBBY B , OSBORNE GORDON C JR , SMITH ROBERT M
Abstract: A semiconductor module includes a semiconductor chip, a lead frame having le ad fingers, and a down set member within an encapsulant for reduce warpage and providing a more planar package by balancing thermal stress between the lead fingers and the encapsulant. The down set member can be a bent portion of the lead frame. It can also be a separate body, such as a dummy semiconductor chip.
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公开(公告)号:MY127450A
公开(公告)日:2006-12-29
申请号:MYPI20004784
申请日:2000-10-12
Applicant: IBM
Inventor: CALETKA DAVID V , JOHNSON ERIC A
Abstract: A METHOD OF FORMING BGA INTERCONNECTIONS HAVING IMPROVED FATIGUE LIFE IS DISCLOSED.IN PARTICULAR,A COMBINATION OF MASK-DEFINED AND PAD-DEFINED SOLDER JOINTS (40,42) ARE SELECTIVELY POSITIONED WITHIN THE BGA PACKAGE (36).THE MASK-DEFINED SOLDER JOINTS POSSESS A HIGH EQUILIBRIUM HEIGHT,WHICH FORCES THE PAD-DEFINED SOLDER JOINTTS TO ELONGATE, THEREBY MAKING THE PAD-DEFINED SOLDER JOINTS MORE COMPLIANT. FURTHER, THE PAD-DEFINED SOLDER JOINTS POSSES A SLIGHTLY LONGER FATIGUE LIFE BECAUSE THE STRESS CONCENTRATIONS FOUND IN THE MASK-DEFINED SOLDER JOINTS ARE NOT PRESENT IN THE PAD-DEFINED SOLDER JOINTS.THEREFORE , THE FATIGUE LIFE OF BGA PACKAGES IS INCREASED BY IMPLEMENTING A MAJORITY OF MASK - DEFINED SOLDER JOINTS TO MAINTAIN A HIGH EQUILIBRIUM HEIGHT,AND SELECTIVELY PLACING PAD-DEFINED SOLDER JOINTS IN HIGH STRESS AREAS OF THE BGA PACKAGE.(FIG. 1)
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公开(公告)号:AU2003251438A1
公开(公告)日:2004-03-11
申请号:AU2003251438
申请日:2003-07-22
Applicant: IBM
Inventor: DARBHA KRISHNA , HENDERSON DONALD W , LEHMAN LAWRENCE P , THIEL GEORGE H , CALETKA DAVID V
IPC: B23K35/14 , B23K35/26 , C22C12/00 , C22C13/02 , H01L21/56 , H01L21/60 , H01L23/485 , H05K3/28 , H05K3/34 , H01R4/00
Abstract: An electronic package is provided including a substrate, a device mounted on the substrate, and a solder member electrically coupling the device to the substrate. The package includes a dielectric material positioned substantially around the solder member which forms a physical connection between the substrate and the device. The volume of the solder member contracts during melting thereof to prevent failure of the physical connection and/or the electrical coupling between the substrate and the device.
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公开(公告)号:BR0102606A
公开(公告)日:2002-02-13
申请号:BR0102606
申请日:2001-06-28
Applicant: IBM
Inventor: CALETKA DAVID V , CARPER JAMES L , CINCOTTA JOHN P , HORSFORD KIBBY B , IRISH GARY H , LAJZA JOHN J JR , OSBORNE GORDON C JR , RAMSEY CHARLES R , SMITH ROBERT M , VADNAIS MICHAEL J
Abstract: A semiconductor module includes a semiconductor chip, a lead frame having lead fingers, and a down set member within an encapsulant for reduce warpage and providing a more planar package by balancing thermal stress between the lead fingers and the encapsulant. The down set member can be a bent portion of the lead frame. It can also be a separate body, such as a dummy semiconductor chip.
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公开(公告)号:MY119889A
公开(公告)日:2005-07-29
申请号:MYPI20012927
申请日:2001-06-21
Applicant: IBM
Inventor: CALETKA DAVID V , VADNAIS MICHAEL J , CARPER JAMES L , CINCOTTA JOHN P , HORSFORD KIBBY B , IRISH GARY H , LAJZA JOHN J JR , OSBORNE GORDON C JR , RAMSEY CHARLES R , SMITH ROBERT M
Abstract: A SEMICONDUCTOR MODULE INCLUDES A SEMICONDUCTOR CHIP, A LEAD FRAME HAVING LEAD FINGERS, AND A DOWN SET MEMBER WITHIN AN ENCAPSULANT FOR REDUCE WARPAGE AND PROVIDING A MORE PLANAR PACKAGE BY BALANCING THERMAL STRESS BETWEEN THE LEAD FINGERS AND THE ENCAPSULANT. THE DOWN SET MEMBER CAN BE A BENT PORTION OF THE LEAD FRAME. IT CAN ALSO BE A SEPARATE BODY, SUCH AS A DUMMY SEMICONDUCTOR CHIP.
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公开(公告)号:HK1042591A1
公开(公告)日:2002-08-16
申请号:HK02104209
申请日:2002-06-03
Applicant: IBM
Inventor: CALETKA DAVID V , CARPER JAMES L , CINCOTTA JOHN P , HORSFORD KIBBY B , IRISH GARY H , LAJZA JOHN J JR , OSBORNE GORDON C JR , RAMSEY CHARLES R , SMITH ROBERT M , VADNAIS MICHAEL J
Abstract: A semiconductor module includes a semiconductor chip, a lead frame having lead fingers, and a down set member within an encapsulant for reduce warpage and providing a more planar package by balancing thermal stress between the lead fingers and the encapsulant. The down set member can be a bent portion of the lead frame. It can also be a separate body, such as a dummy semiconductor chip.
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公开(公告)号:BR0004882A
公开(公告)日:2001-10-02
申请号:BR0004882
申请日:2000-10-17
Applicant: IBM
Inventor: CALETKA DAVID V , JOHNSON ERIC A
Abstract: A method of forming BGA interconnections having improved fatigue life is disclosed. In particular, a combination of mask-defined and pad-defined solder joints are selectively positioned within the BGA package. The mask-defined solder joints possess a high equilibrium height, which forces the pad-defined solder joints to elongate, thereby making the pad-defined solder joints more compliant. Further, the pad-defined solder joints posses a slightly longer fatigue life because the stress concentrations found in the mask-defined solder joints are not present in the pad-defined solder joints. Therefore, the fatigue life of BGA packages is increased by implementing a majority of mask-defined solder joints to maintain a high equilibrium height, and selectively placing pad-defined solder joints in high stress areas of the BGA package.
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