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    High availability, high precision system clock register arrangement
    1.
    发明专利
    High availability, high precision system clock register arrangement 未知

    公开(公告)号：GB2489307A

    公开(公告)日：2012-09-26

    申请号：GB201204158

    申请日：2012-03-09

    Applicant: IBM

    Inventor： GERWIG GUENTER ,  ENGLER EBERHARD ,  BUTTLAR JOACHIM VON ,  MEISSNER KLAUS ,  LEHNERT FRANK

    IPC: G06F1/14 ,  G06F11/16

    Abstract: A time of day (TOD) system clock associated with a processing core (2) comprises a host clock register (5) incremented by means of a high precision oscillator (3) and a firmware clock register (6), incremented every time the host clock register (5) is incremented. The system monitors for failures of the host clock register (5), and during a failure of the host clock register (5) increments the firmware clock register (6) by means of timing signals of the processing core (2). Upon receiving a clock value read request providing the content of the host clock register (5) if no failure is detected and updating the firmware clock register (6) with the value of the host clock register (5).

    Handling inbound initiatives for a multi-processor system by its input/output subsystem using data that defines which processor is to handle it.
    3.
    发明专利
    Handling inbound initiatives for a multi-processor system by its input/output subsystem using data that defines which processor is to handle it. 未知

    公开(公告)号：GB2454996A

    公开(公告)日：2009-05-27

    申请号：GB0822779

    申请日：2008-12-15

    Applicant: IBM

    Inventor： NASS ELKE ,  TAUBERT MARTIN ,  LEHMANN HANS-HELGE ,  BUTTLAR JOACHIM VON ,  KOEBLE FRANK ,  ALBUS ALEXANDER ,  OAKES KENNETH J ,  TROTTER JOHN S

    IPC: G06F9/50

    Abstract: Disclosed is a method for multiprocessor computer systems using an optimized input/output subsystem that is based on dedicated System Assist Processors (SAPs) or I/O Processors (I0Ps) to handle inbound initiatives i.e. request responses and / or external event notifications. Each node (10) of the I/O processors (12) communicates with I/O devices, via I/O paths (2) corresponding to the nodes (10), and the responses are generated by I/O hardware and/or firmware addressed by a precedent I/O request issued by a respective one of said I/O processors (12). The external event notifications are generated by I/O hardware and/or firmware, and the initiatives are to be processed by one or a group of the multiple I/O processors. Using a pre-defined, first data element (20) indicating incoming or existing initiatives from any I/O path (2) of all of the nodes to be served by one of the I/O processors (12), using a second data structure (22), one of the second structures per node (10), wherein each of said second data structures defines which initiative is preferably handled by which processor (12) or group of processors (12), respectively, and using a third data structure (24), one of per node (10), such that multiple bits can be set in order to indicate the occurrence of respective initiatives for respective multiple I/O processors (12).

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